• Journal of information and communication convergence engineering
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• v.2 no.2
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• pp.102-105
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• 2004

A Quadrature phase detector for high-speed delay-locked loop is introduced. The proposed Quadrature phase detector is composed of two nor gates and it determines if the phase difference of two input clocks is 90 degrees or not. The delay locked loop circuit including the Quadrature phase detector is fabricated in a 0.18 um Standard CMOS process and it operates at 5 GHz frequency. The phase error of the delay-locked loop is maximum 2 degrees and the circuits are robust with voltage, temperature variations.

• Journal of Korean Society of Transportation
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• v.14 no.2
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• pp.59-88
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• 1996

This study has determined optimal type, and location of loop detector to measure accurately traffic condition influenced by traffic variation with real time. Optimal type of loop detector for through vehicle at stop bar was determined by confidences of occupancy period, and nonoccupancy period, and so appropriate detector type for application to real time traffic control system has been decided on special loop detector.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.6A
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• pp.685-692
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• 2008

In this paper, we propose a timing recovery loop for Inmarsat mini-m system downlink receiver. Inmarsat mini-m system requires a timing recovery loop which is robust in frequency offset and has fast acquisition because Inmarsat mini-m system specification requires frequency tolerance is required of ${\pm}924$ Hz (signal bandwidth: 2.4 kHz) and acquisition time of UW (Unique Word) signal duration (15ms).Therefore, we propose a timing recovery loop which is suitable for Inmarsat mini-m system. The proposed timing recovery loop adopted noncoherent UW detector and differential ELD which applied differential UW signal for stability and fast acquisition in frequency offset environment. Simulation results show that the proposed timing recovery loop has stable operation and fast acquisition in frequency offset environment for the system.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.29 no.10
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• pp.773-782
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• 2018

A frequency-locked loop(FLL) is a negative-feedback system that uses a frequency detector to improve the phase noise of a voltage-controlled oscillator(VCO). In this work, a theoretical analysis of the phase noise of a VCO in an FLL is presented. The analysis shows that the phase noise of the VCO follows the phase noise determined by the frequency detector and the loop filter within the FLL loop bandwidth, while the phase noise of the VCO appears outside the loop bandwidth. Therefore, it is possible to design an FLL that minimizes the phase noise of the VCO based on the theoretical analysis results. The theoretical phase noise results were verified through experiments.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.12 no.5
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• pp.22-35
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• 2013

With the increase in image detectors, concerns about the reliability of traffic information are increasing. In this paper, we propose a method to generate reliable traffic volume using analysis of the point detector data as a representative value. Therefore, targeting expressway, we analyzed the difference in traffic volume collected by loop and image detector, and verified statistically using t-test, and finally analyzed the error rate compare to the real traffic volume. Analysis revealed that there was a statistically difference the traffic date collected by the loop detector and the image detector, in the same period, the same time, respectively. In addition, the difference between the actual traffic volume and traffic that have been collected in a loop detector was the lowest Therefore, creating a traffic volume of representative value, we proposed a method to use loop detector than the average traffic volume collected by each detector. It shows that it is more important to use one high-quality data rather than various low-quality data to produce a representative value.

• Proceedings of the KIEE Conference
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• 2000.07d
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• pp.2956-2958
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• 2000

This paper describes the design of a real time traffic data acquisition system using loop detector and piezzo sensor. Loop detector is the cheapest method to measure the speed and piezzo is used to detect the vehicle axle information. A ISA slot based I/O board is designed for data acquisition and PC process the raw traffic data and transfer the data to the host system. Simulation kit is designed with toy car kits. simulated loop detector and piezzo sensor. The data acquisition system collects up to 10 lane highway traffic data such as vehicle count. speed. length axle count. distance between the axles. The data is processed to generate traffic count, vehicle classification, which are to be used for ITS. The system architecture and simulation data is included and the system will be tested for field operation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2004.05a
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• pp.28-31
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• 2004

A Quadrature phase detector for high-speed delay-locked loop is introduced. The proposed Quadrature phase detector is composed of two nor gates and it determines if the phase difference of two input clocks is 90 degrees or not. The delay locked loop circuit including the Quadrature phase detector is fabricated in a 0.18 urn standard CMOS process and it operates at 5 ㎓ frequency. The phase error of the delay-locked loop is maximum 2 degrees and the circuits are robust with voltage, temperature variations.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.7
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• pp.540-549
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• 2017

A phase frequency detector(PFD) composed of logic circuits is widely used in a phase locked loop(PLL) due to the easy implementation for integrated circuits. A frequency locked loop(FLL) removes the reference oscillator in the PLL, and the resonator serves as a reference oscillator. A frequency detector(FD) is indispensable for the FLL configuration, and a FD, which is usually composed of a mixer is used to build an FLL. In this paper, instead of FD using mixer, a FD is constructed by using 1.175 GHz resonator composed of microstrip and PFD taking the versatility of PFD into consideration. Using the designed FD, FLL oscillating at a frequency of 1.175 GHz is composed. As a result of comparison with the FLL composed of FD using mixer, it was confirmed that the proposed FLL has better phase noise performance than FLL using mixer FD with FLL bandwidth.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.3
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• pp.598-604
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• 2009

This paper proposes a vehicle detector with an anisotropic magnetoresistive (AMR) sensor and addresses experimental results to show the detector's performance. The detector consists of an AMR sensor and mechanical and electronic apparatuses. The AMR sensor, composed of four magnetoresistors, senses disturbance of the earth's magnetic field caused by a vehicle moving over the sensor and then produces an output indicative of the moving vehicle. This paper verifies performance of the detector on the basis of experimental results obtained from the field tests carried under the two traffic conditions on local highways in Korea. First, I show the vehicle counting performance on a low speed congested highway by comparing the vehicle counts measured by the detector with the exact counts. Second, both vehicle counts and average speeds calculated from the measured point-occupancy on another continuously free running highway are compared with the reference values obtained from a loop detector which has two independent loop coils, where I have used several performance indices including mean absolute percentage error (MAPE) to show the performance consistency between the two types of detectors.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.7C
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• pp.706-714
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• 2009

In this paper, we proposed a burst mode AGC loop and preamble detector applicable for VDL(VHF Digital Link) mode-2 using D8PSK modulation scheme and the performance analysis of proposed schemes is described. Generally the AGC scheme can be divided into two types, continuos and burst mode AGC. The continuos mode is performed well only with an analog feedback AGC loop. But the analog feedback AGC loop is not suitable for burst mode since its gain lock time is more than preamble duration, which causes the preamble detector misses preamble. Hence a fast digital AGC loop is required for burst mode. Also the AGC loop has to be designed with full gain during idle time to detect bursts although the signal level is very low. If the time to acquire gain lock is slow, the preamble detector fail to detect burst due to saturation of a lot of preamble samples. The receiver performance might be down even if the burst was detected because the preamble is used to estimate several parameters need to demodulation at receiver. In this paper we analysed relationships between the AGC loop and preamble detector. we present an AGC loop and preamble detector in burst mode.