• Journal of the Institute of Electronics and Information Engineers
• /
• v.53 no.4
• /
• pp.136-141
• /
• 2016

A phase-locked loop(PLL) with effectively increased capacitance by current modulator has been proposed. In this paper, the effective capacitance of loop filter is increased by using current modulator and it results in 1/10 reduction of capacitance in loop filter. It has been designed with a 1.8V $0.18{\mu}m$ CMOS process. The simulation results show that the proposed PLL has the same phase noise characteristic and locking time of conventional PLL.

• Journal of the Korean Institute of Telematics and Electronics S
• /
• v.35S no.1
• /
• pp.14-22
• /
• 1998

The Mathematic model of bit synchronization charge-pump Phase Locked Loop (PLL) is presented which takes into account the aperiodic reference pulses and the leakage current of the loop filter. We derive theoreitcal static phase error, overload and stability of bit synchronization charge-pump PLL using presented model and compare it with one of the conventional charge-pump PLL model. We can analysis bit synchronization charge-pump PLL exactly because our model takes into account the leakage current of the loop filter and aperiodic input data which are the charateristics of bit synchronization charge-pump PLL. We also verify it using HSPICE simulation with a bity synchronizer circuit.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
• /
• 2003.11a
• /
• pp.224-228
• /
• 2003

In this paper, for phase lock loop(PLL) synthesizer, we introduce a novel but simple and low cost frequency modulation(FM) circuit of a flat peak frequency deviation for modulation signal from high to very low frequency penetrating into the loop-bandwidth of PLL. The FM circuit was basically designed to compensate an amount of feedback of the loop filter in PLL. The circuit also includes the capability of the adjustment of peak frequency deviation and blocking the interference with the loop filter. The designed circuit was successfully implemented and showed the flat frequency deviation as expected in the design.

• Proceedings of the KSME Conference
• /
• 2000.11a
• /
• pp.564-569
• /
• 2000

Model Based Compensator(MBC) is recently used for the analysis of multi-variable control in frequency domain. Target loop is designed by the demanding requirements such as cross-over frequency, disturbance rejection in low frequency domain, zero steady-state error, identification of maximum and minimum singular values and sensor noise rejection in high frequency domain. Loop transfer recovery will be continued in frequency domain until the plant with MBC comes close to the target loop. In this study, the technique using MBC is applied to the elevator vibration control system. It is found that this technique is very effective to control the vibration system.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2016.05a
• /
• pp.698-701
• /
• 2016

A phase-locked loop(PLL) with effectively increased capacitance by current modulator has been proposed. In this paper, the effective capacitance of loop filter is increased by using current modulator and it results in 1/10 reduction of capacitance in loop filter. It has been designed with a 1.8V $0.18{\mu}m$ CMOS process. The simulation results show that the proposed PLL has the same phase noise characteristic and locking time of conventional PLL.

• The Transactions of the Korean Institute of Electrical Engineers B
• /
• v.48 no.9
• /
• pp.461-466
• /
• 1999

The switched reluctance motor (SRM) would have torque ripple if not operated with an MMF waveform specified for switching angle and phase voltage. This paper describes the robustic control scheme that permits the phase torque to be flat by PLL(Phase Locked Loop) controller. In this control scheme, the locked phase signal of PLL controls the switching dwell angle and it's loop filter signal controls the switching voltage adaptively. Experimental results show that stable dynamic performance is obtained for torque and speed together with low torque ripple on the operation of variable loads.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
• /
• v.27 no.12
• /
• pp.10-15
• /
• 2013

In this paper, we propose a Lyot-type optical fiber comb filter based on a polarization-diversity loop structure (PDLS), which has flat-top pass bands and multiwavelength switching capability. Generally, the PDLS can remove the dependency of the filter on input polarization. The proposed filter is composed of a polarization beam splitter, two half-wave plates (HWPs), and two polarization-maintaining fiber loops concatenated with a $60^{\circ}$ offset between their principal axes. By controlling two HWPs, it can operate in a flat-top band mode or a lossy flat-top band mode with an inherent insertion loss of ~3.49dB. In particular, flat-top bands can be interleaved in both modes, which cannot be realized in a Lyot-Sagnac comb filter based on a fiber coupler. Compared with Solc-type high-order comb filters with the same order, the proposed filter shows sharper transition between pass and stop bands.

• Journal of the Korean Society for Aeronautical & Space Sciences
• /
• v.48 no.11
• /
• pp.873-880
• /
• 2020

In this paper, we propose a guidance filter to estimate line of sight rate with strapdown seeker measurements and INS(Inertial Navigation System) information. The measurements of proposed guidance filter consisted of the LOS(Line of Sight) and relative position that can be calculated with the seeker's measurements, INS information and known target position, also the filter is based on an asynchronous filter to use outputs of the two sensors that are out of synchronous and period. Through the proposed filter, we can reduce the effect on parasitic loop that can be caused by using large time delay seeker and improve the estimation performance.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.17 no.10
• /
• pp.2380-2386
• /
• 2013

A PLL with an unipolar charge pump and a loop filter consisting of sample-hold capacitor and 2nd-order RC filter has been proposed. The goal of the proposed PLL is the suppression of reference spur which is caused by charge pump mismatch. It also improves phase noise characteristic. It has been designed with a 1.8V $0.18{\mu}m$ CMOS process and proved by HSPICE simulation.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.22 no.2
• /
• pp.245-251
• /
• 2011

In this paper, dual-band bandpass filter by using Pseudo-Interdigital Stepped-Impedance Resonator(PI-SIR) and Open-Loop Ring Resonator(OLRR) is proposed. The first passband and second passband are formed by PI-SIR and the second passband is reinforced by an OLRR. In a PI-SIR the first band and second band are easily and exactly adjusted by characteristic impedance ratio and electrical length ratio. The proposed design method may be confirmed to be useful from fabricated and measured results for dual-band bandpass filter operated at 2.45 GHz and 5.8 GHz.