• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.42 no.10
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• pp.884-892
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• 2014

In this paper, a meta model using neural network substituting for the simulator aerodynamic database is proposed to improve simulation fidelity near the critical flight area and real-time performance. It is shown that the accuracy of the meta model is relatively higher than the existing table lookup methods for arbitrary nonlinear database and the calculation speed is also improved for a specific F-16 maneuver simulation. The increase in the number of hidden nodes in the meta model for better accuracy of database representations causes a delay in function generation due to increased time required for computing exponential functions. In order to make up this drawback, we additionally study the fast exponential function method.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.3
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• pp.633-637
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• 2005

In this contribution, we developed and improved an existing GF (Galois field) dividing algorithm by suggesting a novel architecture for a finite field divider, which is frequently required for the error correction applications and the security-related applications such as the Reed-Solomon code, elliptic curve encryption/ decryption, is proposed. We utilized the VHDL language to verify the design methodology, and implemented the architecture on an FPGA chip. We suggested the n-bit lookup table method to obtain the throughput of 2m/n cycles, where m is the order of the division polynomial and n is the number of the most significant lookup-bits. By doing this, we extracted the advantages in achieving both high-throughput and less cost of the gate areaon the chip. A pilot FPGA chip was implemented with the case of m=4, n=2. We successfully utilized the Altera's EP20K30ETC144-1 to exhibit the maximum operating clock frequency of 77 MHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.4
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• pp.798-803
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• 2005

This paper describes a design of AES(Advanced Encryption Standard)-based CCMP core for IEEE 802.1li wireless LAN security. To maximize its performance, two AES cores ate used, one is for counter mode for data confidentiality and the other is for CBC(Cipher Block Chaining) mode for authentication and data integrity. The S-box that requires the largest hardware in AES core is implemented using composite field arithmetic, and the gate count is reduced by about $20\%$ compared with conventional LUT(Lookup Table)-based design. The CCMP core designed in Verilog-HDL has 13,360 gates, and the estimated throughput is about 168 Mbps at 54-MHz clock frequency. The functionality of the CCMP core is verified by Excalibur SoC implementation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.6A
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• pp.640-647
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• 2006

This paper describes a design of AES-based CCMP(Counter mode with CBC-MAC Protocol) core for IEEE 802.11i wireless LAN security. To maximize the performance of CCMP core, two AES cores are used, one is the counter mode for data confidentiality and the other is the CBC node for authentication and data integrity. The S-box that requires the largest hardware in ARS core is implemented using composite field arithmetic, and the gate count is reduced by about 27% compared with conventional LUT(Lookup Table)-based design. The CCMP core was verified using Excalibur SoC kit, and a MPW chip is fabricated using a 0.35-um CMOS standard cell technology. The test results show that all the function of the fabricated chip works correctly. The CCMP processor has 17,000 gates, and the estimated throughput is about 353-Mbps at 116-MHz@3.3V, satisfying 54-Mbps data rate of the IEEE 802.11a and 802.11g specifications.

• Journal of the Korea Society of Computer and Information
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• v.17 no.12
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• pp.71-82
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• 2012

In this paper, we propose a license plate detection method with improved Adaboost learning and MCT (Modified Census Transform). The MCT represents the local structure patterns as integer numbered feature values which has robustness to illumination change and memory efficiency. However, since these integer values are discrete, a lookup table is needed to design a weak classifier for Adaboost learning. Some previous research efforts have focused on minimization of exponential criterion for Adaboost optimization. In this paper, a method that uses MCT and improved Adaboost learning based on Newton's optimization to exponential criterion is proposed for license plate detection. Experimental results on license patch images and field images demonstrate that the proposed method yields higher performance of detection rates with low false positives than the conventional method using the original Adaboost learning.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.1
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• pp.367-370
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• 2005

This paper describes a design of AES(Advanced Encryption Standard)-based CCMP core for IEEE 802.11i wireless LAN security. To maximize its performance, two AES cores are used, one is for counter mode for data confidentiality and the other is for CBC(Cipher Block Chaining)mode for authentication and data integrity. The S-box that requires the largest hardware in AES core is implemented using composite field arithmetic, and the gate count is reduced by about 25% compared with conventional LUT(Lookup Table)-based design. The CCMP core designed in Verilog-HDL has 15,450 gates, and the estimated throughput is about 128 Mbps at 50-MHz clock frequency). The functionality of the CCMP core is verified by Excalibur SoC implementation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.7
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• pp.1332-1340
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• 2007

This paper describes an efficient hardware design of key wrap/unwrap algorithm for security layer of WiBro system. The key wrap/unwrap core (WB_KeyWuW) is based on AES (Advanced Encryption Standard) algorithm, and performs encryption/decryption of 128bit TEK (Traffic Encryption Key) with 128bit KEK (Key Encryption Key). In order to achieve m area-efficient implementation, two design techniques are considered; First, round transformation block within AES core is designed using a shared structure for encryption/decryption. Secondly, SubByte/InvSubByte blocks that require the largest hardware in AES core are implemented by using field transformation technique. As a result, the gate count of the WB_KeyWuW core is reduced by about 25% compared with conventional LUT (Lookup Table)-based design. The WB_KeyWuW con designed in Verilog-HDL has about 14,300 gates, and the estimated throughput is about $16{\sim}22-Mbps$ at 100-MHz@3.3V, thus the designed core can be used as an IP for the hardware design of WiBro security system.

• Journal of the Korea Society of Computer and Information
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• v.15 no.12
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• pp.93-100
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• 2010

In this paper, we propose a technique which makes it faster to delete prefixes in an IP address lookup architecture based on parallel TCAMs. In previous deletion schemes, more than one memory movement is needed for the prefix ordering and keeping the available memory space consecutive. For deletion, our scheme stores the address of the deleted prefix in a stack implemented by SRAM instead of actual movement in TCAM. Since SRAM has very short latency compared to TCAM, the proposed scheme can accomplish fast updating. From the experiment with the real forwarding table and update trace, we evaluate the performance of our scheme in terms of the memory access time for the prefix insertion and deletion. The experiment result also shows good performance with considerably small size of stack.

• 한국HCI학회:학술대회논문집
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• 2009.02a
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• pp.232-239
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• 2009

Emerging social networking services provide a new paradigm for human-to-human communication. However, these services are centralized and managed by single service provider. In this paper, we propose MicroPost, a decentralized event notification service architecture for social applications based on publish/subscribe model. In our design space, event brokers are structured as an overlay network which provides the substrate of distributed peer-to-peer lookup service for storing and retrieving subscriptions with hashed keys. Event clients interact with event brokers to publish or subscribe social messages over the wide-area network. Using XML standards, we present an efficient algorithm to forward events for rendezvous-based matching in this paper. In our design space, the cost of routing is O(${\omega}log_kN$), where N is the number of event brokers, ${\omega}$ is the number of meta-data obtained from event messages, and k is a constant, which is selected by our design, to divide the identifier space and to conquer the lookup of given key. Consequently, what we achieved is an asynchronous social messaging service architecture which is decentralized, efficient, scalable, and flexible.

• Journal of Digital Contents Society
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• v.5 no.3
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• pp.219-224
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• 2004

In This paper, we have analyzed the power spectrum of DS-TH Ulhawideband (Direct Sequence-Time Hopping UWB) system which used pseudo-noise (PN) code. The DS-TH UWB system proposed in this paper multiplies the information signal with PN code to construct pulse train with random pattern and then the chips in pulse train are bundled into several groups to map to the particular value. The (+)/(-) pulse is tented in the time slot of frame by comparing a particular value with timing information that was stored in the lookup table. Thus, the energy spark (Comb Line) which is generated certainly in convantional system can be suppressed efficiently by PN code. And we knew that the proposed DS-TH UWB System even could have very smoothing power spectrum ctaracteristic without applying high speed Time-Hopping code.