• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.12
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• pp.1878-1888
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• 1990

In this paper, the input-output interconnection method of the multi-valued signal processing circuit using perfect Shuffle technique and Kronecker product is discussed. Using this method, the design method of circuit of the multi-valued Reed-Muller expansions(MRME) to be used the multi-valued signal processing on finite field GF(p**m) is presented. The proposed input-output interconnection method is shown that the matrix transform is efficient and that the module structure is easy. The circuit design of MRME on FG(p**m) is realized following as` 1) contructing the baisc gates on GF(3) by CMOS T gate, 2) designing the basic cells to be implemented the transform and inverse transform matrix of MRME using these basic gates, 3) interconnecting these cells by the input-output interconnecting method of the multivalued signal processing circuits. Also, the circuit design of the multi-valued signal processing function on GF(3\ulcorner similar to Winograd algorithm of 3x3 array of DFT (discrete fourier transform) is realized by interconnection of Perfect Shuffle technique and Kronecker product. The presented multi-valued signal processing circuits that are simple and regular for wire routing and posses the properties of concurrency and modularity are suitable for VLSI.

• Journal of Korea Society of Industrial Information Systems
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• v.22 no.1
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• pp.53-59
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• 2017

This Paper Proposes a New High-speed Design Methodology for Delay Insensitive Asynchronous Circuits Combining with a Pseudo-NMOS Structure used for High Performance in Synchronous Circuits. Null Convention Logic(NCL) of Conventional Delay-Insensitive Asynchronous Design Methodologies has many Advantages of High Reliability, Low Power Consumption, and Easy Design Reuses not Dependant on Semiconductor Technology. However. the Conventional NCL Gates has a Complicated Stack Structure, so it Suffers from Increased Circuit Delay. Therefore, a New NCL Gates and its Pipeline Structure for High Performance, and the Proposed Methodology has been Designed and Evaluated by a $4{\times}4$ Multiplier Designed using SK-Hynix 0.18 um CMOS Technology. The Experimental Results are Compared with a Conventional NCL in Terms of Power and Delay and shows that the Propagation Delay of the Proposed Multiplier is Reduced by 85% Compared with the Conventional NCL Multiplier.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.12
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• pp.209-218
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• 2012

Recently, the Field Programmable Stateful Logic Array (FPSLA) was proposed as one of the most promising system integration technologies which will extend the life of the Moore's law. This work is the first proposal of the FPSLA design automation flow, and the approaches to logic synthesis, synchronization, physical mapping, and automatic placement of the FPSLA designs. The synchronization at each gate for pipelining determines the x-coordinates of cells, and reduces the placement to 1-dimensional problems. The objective function and its gradients for the non-linear optimization of the net length and placement density have been remodeled for the reduced global placement problem. Also, a recursive algorithm has been proposed to legalize the placement by relaxing the density overflow of bipartite bin groups in a top-down hierarchical fashion. The proposed model and algorithm are implemented, and validated by applying them to the ACM/SIGDA benchmark designs. The output state of a gate in an FPSLA needs to be duplicated so that each fanout gate can be connected to a dedicated copy. This property has been taken into account by merging the duplicated nets into a hyperedge, and then, splitting the hyperedge into edges as the optimization progresses. This yields additional 18.4% of the cell count reduction in the most dense logic stage. The practicality of the FPSLA can be further enhanced primarily by incorporating into the logic synthesis the constraint to avoid the concentrated fains of gates on some logic stages. In addition, an efficient algorithm needs to be devised for the routing problem which is based on a complicated graph. The graph models the nanowire crossbar which is trimmed to be embedded into the FPSLA fabric, and therefore, asymmetric. These CAD tools can be used to evaluate the fabric efficiency during the architecture enhancement as well as automate the design.

• Korean Journal of Optics and Photonics
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• v.19 no.1
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• pp.60-67
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• 2008

An all-optical 4-bit Gray code to binary coded decimal (BCD) converter by means of commercially available numerical analysis tool (VPI) was demonstrated, for the first time to our knowledge. Circuit design approach was modified appropriately in order to fit the electrical method on an all-optical logic circuit based on a cross gain modulation (XGM) process so that signal degradation due to the non-ideal optical logic gates can be minimized. Without regenerations, Q-factor of around 4 was obtained for the most severely degraded output bit (least significant bit-LSB) with 2.5 Gbps clean input signals having 20 dB extinction ratio. While modifying the two-level simplification method and Karnaugh map method to design a Gray code to BCD converter, a general design concept was also founded (one-level simplification) in this research, not only for the Gray code to BCD converter but also for any general applications.

• Journal of Construction Engineering and Project Management
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• v.8 no.4
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• pp.1-24
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• 2018

In the last decade, the use of Building Information Modeling (BIM) as a new technology has been applied with traditional Computer-aided design implementations in an increasing number of architecture, engineering, and construction projects and applications. Its employment alongside construction management, can be a valuable tool in helping move these activities and projects forward in a more efficient and time-effective manner. The traditional stakeholders, i.e., Owner, A/E and the Contractor are involved in this BIM system that is used in almost every activity of construction projects, such as design, cost estimate and scheduling. This article extracts major features of the application of BIM from perspective of participating BIM components, along with the different phrases, and applies to them a logistic analysis using a fuzzy performance tree, quantifying these phrases to judge the effectiveness of the BIM techniques employed. That is to say, these fuzzy performance trees with fuzzy logic concepts can properly translate the linguistic rating into numeric expressions, and are thus employed in evaluating the influence of BIM applications as a mathematical process. The rotational fuzzy models are used to represent the membership functions of the performance values and their corresponding weights. Illustrations of the use of this fuzzy BIM performance tree are presented in the study for the uninitiated users. The results of these processes are an evaluation of BIM project performance as highly positive. The quantification of the performance ratings for the individual factors is a significant contributor to this assessment, capable of parsing vernacular language into numerical data for a more accurate and precise use in performance analysis. It is hoped that fuzzy performance trees and fuzzy set analysis can be used as a tool for the quality and risk analysis for other construction techniques in the future. Baldwin's rotational models are used to represent the membership functions of the fuzzy sets. Three scenarios are presented using fuzzy MEAN, AND and OR gates from the lowest to intermediate levels of the tree, and fuzzy SUM gate to relate the intermediate level to the top component of the tree, i.e., BIM application final performance. The use of fuzzy MEAN for lower levels and fuzzy SUM gates to reach the top level suggests the most realistic and accurate results. The methodology (fuzzy performance tree) described in this paper is appropriate to implement in today's construction industry when limited objective data is presented and it is heavily relied on experts' subjective judgment.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.9A
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• pp.1442-1450
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• 1999

In this paper, we present an efficient hardware architecture for the frame memory of the MPEG-2 video encoder. Both the total size of internal buffers and the number of logic gates are reduced by the proposed memory map which can provide an effective interface between MPEG-2 video encoder and the external DRAM. Furthermore, the proposed scheme can reduce the DRAM access time. To realize the frame memory hardware,$0.5\mu\textrm{m}$, VTI, vemn5a3 standard cell library is used. VHDL simulator and logic synthesis tool are used for hardware design and RTL (register transfer level) function verification. The frame memory hardware emulator of the proposed architecture is designed for gate-level function verification. It is expected that the proposed frame memory hardware using VHDL can achieve suitable performance for MPEG-2 MP@ML.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.10
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• pp.29-38
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• 1999

This paper presents a new algorithm RICP(Redundancy Identification using Critical-pair Paths) to identify untestable faults in combinational logic circuits. In a combinational logic circuit, untestable faults occurred by redundancy of circuits. The redundancy of a circuit can be detected by analyzing areas of fanout stem and reconvergent gates. The untestable faults are identified by analyzing stem area using Critical-Pair path which is an extended concept of critical path. It is showed that RICP is better than FIRE(Fault Independent REdundancy identification) algorithm in efficiency. The performance of both algorithms was compared using ISCAS85 bench mark testing circuits.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.6
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• pp.37-43
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• 1999

Two-way addressing method has been proposed for efficient VLSI implementation of Euclidean calculation circuit for pipelined Reed-Solomon decoder. This new circuit is operating with single clock while exploiting maximum parallelism, and uses register addressing instead of register shifting to minimize the switching power. Logic synthesis shows the circuit with the new scheme takes 3,000 logic gates, which is about 40% reduction from the previous 5,000 gate implementation. Computer simulation also shows the power consumption is about 3mW. The previous implementation with multiple clock consumed about 5mW.

• Journal of Korea Society of Digital Industry and Information Management
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• v.9 no.2
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• pp.55-61
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• 2013

A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a customer or a designer after manufacturing. The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an application-specific integrated circuit (ASIC) (circuit diagrams were previously used to specify the configuration, as they were for ASICs, but this is increasingly rare). Contemporary FPGAs have large resources of logic gates and RAM blocks to implement complex digital computations. In this paper, we implement a system of digital instrumentation using FPGA. This system consists of the trigger part, memory address controller part, control FSM part, Encoder part, LCD controller part. The hardware implement using FPGA and the verification of the operation is done in a PC simulation. The proposed hardware was mapped into Cyclone III EP2C5Q208 from Altera and used 1,700(40%) of Logic Element (LE). The implemented circuit used 24,576-bit memory element with 6-bit input signal. The result from implementing in hardware (FPGA) could operate stably in 140MHz.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.2
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• pp.168-176
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• 2015

Due to the reduction in device feature size, transient faults (soft errors) in logic circuits induced by radiations increase dramatically. Many researches have been done in modeling and analyzing the susceptibility of sequential circuit elements caused by soft errors. However, to the best knowledge of the authors, there is no work which has well considerated the feedback characteristics and the multiple clock cycles of sequential circuits. In this paper, we present a new method for evaluating the susceptibility of sequential circuit elements to soft errors. The proposed method uses four Error Propagation Probability Matrixs (EPPMs) to represent the error propagation probability of logic gates and flip-flops in current clock cycle. Based on the predefined matrix union operations, the susceptibility of circuit elements in multiple clock cycles can be evaluated. Experimental results on ISCAS'89 benchmark circuits show that our method is more accurate and efficient than previous methods.