• Journal of The Korean Association of Information Education
• /
• v.13 no.3
• /
• pp.341-349
• /
• 2009

In this paper, we proposed an Electric Circuit manipulation method to identify easily results of Digital Logic Circuits. Using this method for computer science educations, we can feasibly instruct and understand principles of a Digital Logic Circuit which is a basis of real Digital systems. Furthermore, we developed an PBL-based education program for Digital Logic Circuit concept and Boolean Algebra concept by applying the proposed Electric Circuit manipulation method and by explaining real life Digital Instrument examples. The experimental results are analyzed in views of the problem-solving ability and suitability of allocating degrees of difficulties to the developed Digital Logic Circuit problems.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.33A no.6
• /
• pp.230-238
• /
• 1996

In this paper, digital corrction and calibration circuit for a high-resolution CMOS pipelined A/D converter are proposed. The circuits were actually applied to a 12 -bit 4-stage pipelined A/D converter which was implemented in a 0.8${\mu}$m p-well CMOS process. The proposed digital correction logic is based on optimum multiplexer and two nonoverlapping clock phases resulting in a small die area snd a modular pipelined architecture. The propsoed digital calibration logic which consists of calibration control logic, error averaging logic, and memory can effectively perform self-calibration with little modifying analog functional bolcks of a conventional pipelined A/D conveter.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.17 no.6
• /
• pp.93-98
• /
• 1980

In this paper, the principles of cascade realization o( conservative logic circuits are explored and the problem of realizing arbitrary 3-3 logic circuit with mini mal number of logic elements is handled, The five primitive classes 5, 15, 21, 24 and 29 are selected to realize all of the 31 equivalent c]asses by cascading only two of them. The crossovers of lines are permitted in this realization 3nd the upper bound of crossovers is three. The results are summarized and listed in a table.

• Journal of Advanced Marine Engineering and Technology
• /
• v.28 no.5
• /
• pp.793-800
• /
• 2004

The purpose of this study is to develope a servo system with faster and more accurate response. This paper describes a method of approximate reasoning for fuzzy control of servo system based on the decomposition of $\alpha$-level fuzzy sets. We propose that fuzzy logic algorithm is a body from fuzzy inference to defuzzificaion cases where the output variable u directly is generated PWM The effectiveness for robust and faster response of the fuzzy control scheme are verified for a variable parameter by comparison with a PID control and fuzzy control A position control of DC servo system with a fuzzy logic controller is demonstrated successfully.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.13 no.5
• /
• pp.411-421
• /
• 1988

This paper offers a method to design CCD four-valued circuits using the tabular method. First, the four-valued logic function is decomposed by hand-calculation or computer program. Nest, the algorithm is derived form the tabular method based on the decomposition process to realize the DDC four-valued circuit. According to this algorithm, the two-variable four valued logic function is decomposed and realized by CCD network with four basic gates. The synthesis method in this paper proves that the number of devices and cost is considerably reduces as compared with the existing methods to realize the same logic functions.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.33A no.3
• /
• pp.187-195
• /
• 1996

This paper proposes two new dynamic CMOS logic styles, called ZMODL (zipper-MODL) and EZMODL (enhanced-ZMODL), which can reduce more area dnd propagation delya than conventional MODL (multiple output domino logic). The 32-bit CLAs(carry look-ahead adder) are designed by ZMODL, EZMODL circuits, and their operations are verified by SPICE 3 with 2$\mu$ double metal CMOS parameters. The results shwo that the CLA designed by EZMODL circuit has achived 32-bit additin time of less than 4.8NS with VDD=5.0V and 8% of transistors cn be redcued, compared to the CLA designed by MODL. The EZMODL logic style can improve the performance in the high-speed computing circuits depending on the degree of recurrence.

• The Transactions of the Korean Institute of Electrical Engineers
• /
• v.32 no.4
• /
• pp.109-120
• /
• 1983

This paper presents standard program which can be used in the software realizations of sequential logic circuits. Thy are simple, flexible, and independent of applications and operate in the same way that man decides next states and outputs using the state transition table. With proposed programs, designers who aren't familiar with microprocessors and programming techniques will be able to design sequential logic circuits easily. Examples are illustrated, in order to prove their flexibility and adaptability, using Z-80 microprocessor.

• Proceedings of the IEEK Conference
• /
• 1998.10a
• /
• pp.787-790
• /
• 1998

In this paper, we presents a method for multi-level logic mainmization which is suitable for the minimization of look-up table type FPGAs. A pattern extraction algorithm is minimized AND/XOR multi-level circuits. The circuits apply to Roth-Karp decomposition which is most commonly used technique in the FPGA technology mapping. We tested the FPGA synthesis method using pattern extraction on a set of benchmark. The proposed method achieved reductions on the number of LUTs in mapping soultion as compared with MISII(or SIS) or previous results〔5〕

• Proceedings of the IEEK Conference
• /
• 1999.06a
• /
• pp.247-250
• /
• 1999

This paper presents characteristics of neuron-MOSFET for the implementation of logic circuits such at the inverter and D/A converter. Neuron-MOSFETS were fabricated using double poly CMOS process. From the measured results, it was found that noise margin of the inverter was dependant on the coupling ratio and a complete D/A characteristics of the source follower could be obtained by using any input Sate as a control gate.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.35C no.4
• /
• pp.1-10
• /
• 1998

Partitioning problem of large combinational logic has been studied in real world. Most of logic include undectable faults from the structure of it's redundant, fan-out-reconvergent, and symetrical feature. BPT algorithm is proposed to enhance the fault voverage for combinational logic partitioning. This algorithm partitions the logic by cut the lines related to undetectable structure when seperating. Controllability and observability are considered in the process of partitioning. This algorithm is evaluated effective by testing ISCAS85 circuits.