Logic Synthesis for LUT-Type FPGA Using Pattern Extraction

패턴 추출을 이용한 LUT형 FPGA 합성

In this paper, we presents a method for multi-level logic mainmization which is suitable for the minimization of look-up table type FPGAs. A pattern extraction algorithm is minimized AND/XOR multi-level circuits. The circuits apply to Roth-Karp decomposition which is most commonly used technique in the FPGA technology mapping. We tested the FPGA synthesis method using pattern extraction on a set of benchmark. The proposed method achieved reductions on the number of LUTs in mapping soultion as compared with MISII(or SIS) or previous results〔5〕