• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.30 no.7
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• pp.437-440
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• 2017

We report on amorphous thin-film transistors (TFTs) with indium zinc oxide (IZO) channel layers that were fabricated via a solution process. We prepared the IZO semiconductor solution with 0.1 M indium nitrate hydrate and 0.1 M zinc acetate dehydrate as precursor solutions. The solution- processed IZO TFTs showed good performance: a field-effect mobility of $7.29cm^2/Vs$, a threshold voltage of 4.66 V, a subthreshold slope of 0.48 V/dec, and a current on-to-off ratio of $1.62{\times}10^5$. To investigate the static response of our solution-processed IZO TFTs, simple resistor load-type inverters were fabricated by connecting a $2-M{\Omega}$ resistor. Our IZOTFTbased N-MOS inverter performed well at operating voltage, and therefore, isa good candidate for advanced logic circuits and display backplane.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.48-55
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• 2010

As the complexity and the clock speed of semiconductor integrated circuits increase, silicon validation becomes important. In this research, we developed new post-silicon repair & revision techniques to reduce cost and time-to-market. Spare cells are fabricated with the original design and are used for repair when necessary. The interconnections are modified by repair layer revision. The repair cost can be reduced by logic partitioning. Experimental results show that these techniques are effective for low-cost and fast turnaround repair.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.11
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• pp.67-73
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• 2000

The state assignment for a finite state machine greatly affects the delay, area, and testabilities of the sequential circuits. In order to minimize the dependencies among groups of state variables, therefore possibly to reduce the length and number of feedback cycles, a new state assignment technique based on m-block partition is introduced in this paper. After the completion of proposed state assignment and logic synthesis, partial scan design is performed to choose minimal number of scan flip-flops. Experiment shows drastic improvement in testabilities while preserving low area and delay overhead.

• Journal of The Korean Astronomical Society
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• v.29 no.spc1
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• pp.389-390
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• 1996

The CCDs are widely used in astronomical observations either in direct imaging use or spectroscopic mode. However, the areas of available sensors are too small for large imaging format. One possibility to obtain large detection area is to assemble mosaics of CCD, and drive them simultaneously. Parallel driving of many CCDs together rules out the possibility of individual tuning; however, such optimisation is very important, when the ultimate low light level performance is required, particularly for new, or mixed devices. In this work, a new concept is explored for an entirely novel approach, where the drive waveforms are multiplexed and interleaved. This simultaneously reduces the number of leadout connections and permits individual optimisation efficiently. The digital controller can be designed within a single EPLD (Erasable Programmable Logic Device) chip produced by a CAD software package, where most of the digital controller circuits are integrated. This method can minimise the component. count., and improve the system efficiency greatly, based on earlier works by Han et a1. (1996, 1994). The system software has an open architecture to permit convenient modification by the user, to fit their specific purposes. Some variable system control parameters can be selected by a user with a wider range of choice. The digital controller design concept allows great flexibility of system parameters by the software, specifically for the compatibility to deal with any number of mixed CCDs, and in any format, within the practical limit.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.3
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• pp.31-39
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• 1990

An optimization problem of AND-EXOR PLA's with input decoders can be regarded as a minimization problem of Exclusive-Or Sum-Of-Products expressions (ESOP's) for multiple-valued input two-valued output functions. In this paper, We propose a minimization algorithm for ESOP's. The algorithm is based on an iterative improvement. Five rules are used to replace a pair of products with another one. We minimized many ESOP's for arithmetic circuits. In most cases, ESOP's required fewer products than SOP's to realized same functions.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.4
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• pp.39-48
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• 2009

Asynchronous sequential machines, or clockless logic circuits, have several advantages over synchronous machines such as fast operation speed, low power consumption, etc. In this paper, we propose a novel robust controller for input/output asynchronous sequential machines with uncertain state transitions. Due to model uncertainties or inner failures, the state transition function of the considered asynchronous machine is not completely known. In this study, we present a formulation to model this kind of asynchronous machines ana using generalized reachability matrices, we address the condition for the existence of an appropriate controller such that the closed-loop behavior matches that of a prescribed model. Based on the previous research results, we sketch design procedure of the proposed controller and analyze the stable-state operation of the closed-loop system.

• Journal of information and communication convergence engineering
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• v.14 no.4
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• pp.258-267
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• 2016

Three-dimensional integrated circuits (3D ICs) experience die-to-die variations in addition to the already challenging within-die variations. This adds an additional design complexity and makes variation estimation and full-chip optimization even more challenging. In this paper, we show that the industry standard on-chip variation (AOCV) tables cannot be applied directly to 3D paths that are spanning multiple dies. We develop a new machine learning-based model and methodology for an accurate variation estimation of logic paths in 3D designs. Our model makes use of key parameters extracted from existing GDSII 3D IC design and sign-off simulation database. Thus, it requires no runtime overhead when compared to AOCV analysis while achieving an average accuracy of 90% in variation evaluation. By using our model in a full-chip variation-aware 3D IC physical design flow, we obtain up to 16% improvement in critical path delay under variations, which is verified with detailed Monte Carlo simulations.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.1C
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• pp.96-102
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• 2002

Current testing(Iddq testing) on monitoring the quiescent power supply current is an efficient and effective method for CMOS bridging faults. The applicability of this technique, however, requires careful examination. Since cardinality of bridging fault is O($n^2$) and current testing requires much longer testing time than voltage testing, it is important to note that a bridging fault is untestable if the two bridged nodes have the same logic values at all times. Such faults should be identified by a good ATPG tool; otherwise, the fault coverage can become skewed. In this paper, we present an object-oriented redundant fault detection scheme for efficient current testing. Experimental results for ISCAS benchmark circuits show that the improved method is more effective than the previous ones.

• Journal of Korea Society of Industrial Information Systems
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• v.19 no.2
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• pp.37-43
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• 2014

In this paper, we present the effect of forward current gain on emitter area in NPN transistors are used widely in the almost linear integrated circuits and integrated injection logic. Relations between forward current gain and emitter area were conformed with the simulation with examined calculation and experiments. At the same emitter length, as junction depth is increased, common emitter current gain is decreased. Ratio of Emitter bottom area comparing to side area increases, the emitter current gain is increased. The theory and simulation results were fitted in with the experimental data very well.

• Journal of Magnetics
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• v.8 no.1
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• pp.24-31
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• 2003

The discoveries of antiferromagnetic coupling in Fe/Cr multilayers by Grunberg, the Giant Magneto Resistance by Fert and Grunberg and a large tunneling magnetoresistance at room temperature by Moodera have triggered enormous research on magnetic thin films and magnetoelectronic devices. Large opportunities are especially opened by the spin dependent tunneling resistance, where a strong dependence of the tunneling current on an external magnetic field can be found. We will briefly address important basic properties of these junctions like thermal, magnetic and dielectric stability and discuss scaling issues down to junction sizes below 0.01 $\mu\textrm{m}$$^2$with respect to single domain behavior, switching properties and edge coupling effects. The second part will give an overview on applications beyond the use of the tunneling elements as storage cells in MRAMs. This concerns mainly field programmable logic circuits, where we demonstrate the clocked operation of a programmed AND gate. The second 'unconventional' feature is the use as sensing elements in DNA or protein biochips, where molecules marked magnetically with commercial beads can be detected via the dipole stray field in a highly sensitive and relatively simple way.