• Korean Institute of Interior Design Journal
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• v.16 no.4
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• pp.110-118
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• 2007

Technology has been viewed at various stages of civilization as leading to future progress. The building, its services systems and management of the work process all contribute to the well-being of people within an organization. Productivity relies on there being a general sense of high morale and satisfaction with the workplace. Now buildings are considered as providing a milieu for human creativity. Flexibility, adaptability, service integration and high standards of finishes offer an intelligence threshold. Building Automation System(BAS) - controlled lighting systems may offer incremental energy saving. Conventional Lighting control systems often control equipment in a single room or over the limited area, because they are centralized control systems, which means that all the controlled circuits must be wired to a single control panel. The computers used by these systems are typically dedicated microprocess that perform only lighting control functions. By comparison, modern Building automation systems are distributed control system, which means that their computing hardware and software are distributed as a network that microprocessor-based control modules and standard PC. PLC(Programmable Logic controller) is extensible virtually without limits, so that all the lighting in a facility can be controlled by single, unified system - the same system that also can control and monitor the building's HVAC, security, and manufacturing processed, elevators, and more. A Building automation system can control light using schedules, manual controls, occupancy sensors, and photosensors, either singly or in combination. Building Lighting control and monitoring system will be for a energy saving and efficient building management system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.1
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• pp.79-85
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• 2001

In this paper, we propose a new technology mapping algorithm for CPLD consider area under time constraint(TMFCPLD). This technology mapping algorithm detect feedbacks from boolean networks, then variables that have feedback are replaced to temporary variables. Creating the temporary variables transform sequential circuit to combinational circuit. The transformed circuits are represented to DAG. After traversing all nodes in DAG, the nodes that have output edges more than two are replicated and reconstructed to fanout free tree. This method is for reason to reduce area and improve total run time of circuits by TEMPLA proposed previously. Using time constraints and delay time of device, the number of graph partitionable multi-level is decided. Initial cost of each node are the number of OR-terms that it have. Among mappable clusters, clusters of which the number of multi-level is least is selected, and the graph is partitioned. Several nodes in partitioned clusters are merged by collapsing, and are fitted to the number of OR-terms in a given CLB by bin packing. Proposed algorithm have been applied to MCNC logic synthesis benchmark circuits, and have reduced the number of CLBs by 62.2% than those of DDMAP. And reduced the number of CLBs by 17.6% than those of TEMPLA, and reduced the number of CLBs by 4.7% than those of TMCPLD. This results will give much efficiency to technology mapping for CPLDs.

• Proceedings of the KSR Conference
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• 2011.05a
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• pp.1618-1628
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• 2011

The Train Diagnostic and Control System(TDCS) has been equipped on the modern Metro Vehicle, Locomotive and High Speed Train. The main purpose of this system is to support the identification of train status by real-time, the fast action against such failure events during revenue service and the fast convenient maintenance processes. Some of newest TCMS, a kind of control and monitoring system, has participated in the main control functions such as pantograph up and down, powering and braking command and so on. But these kind of control functions of the high speed train which has the operating speed over 300km/h are conducted by the train electrical logic circuits. The KTX-I and KTX-II - the local high speed train, are the typical example. The next generation TDCS for the ongoing project of distributed high speed train(HEMU) is designing with the target to increase main train control functions, to increase the reliability/avalibility and to increase the convenient driving. This paper introduces the overall configurations and functions of the new generation TDCS.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.3
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• pp.215-224
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• 2003

This paper presents an electronic ballast using a novel complex modulation method for the metal halide lamp. The proposed modulation method, which has a modulating signal of swept complex frequency, can eliminate the acoustic resonance more effectively than the conventional modulation method, which has a modulating signal of constant frequency. For the purpose of future application specific integrated circuits (ASIC). the controller of the proposed ballast has been designed only with erasable programmable logic devices (EPLDs), but without a microprocessor. In this paper, detailed proposed modulation schemes are described and experimental results on the proto type 150W metal halide lamp ballast with the proposed modulation method ate discussed.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.4
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• pp.65-72
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• 2013

This paper presents design methodology for Memristor-CMOS circuits and its application to primitive IPs design. We proposed a Memristor model and designed basic elements, Memristor AND/OR gates. The primitive IPs based on a Memristor-CMOS technology is proposed for a Memristive system design. The netlists of IPs are extracted from the layouts of Memristor-CMOS and is verified with SPICE-like Memristor model under $0.18{\mu}m$ CMOS technology. As a result, an example design Memristor-CMOS full adder has only 47.6 % of silicon area compare to the CMOS full-adder.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.290.2-290.2
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• 2016

Recently, organic thin-film transistors have been widely researched for organic light-emitting diode panels, memory devices, logic circuits for flexible display because of its virtue of mechanical flexibility, low fabrication cost, low process temperature, and large area production. In order to achieve high performance OTFTs, increase in accumulation carrier mobility is a critical factor. Post-fabrication thermal annealing process has been known as one of the methods to achieve this by improving the crystal quality of organic semiconductor materials In this paper, we researched the properties of pentacene films with X-Ray Diffraction (XRD) and Atomic Force Microscope (AFM) analyses as different annealing temperature in N2 ambient. Electrical characterization of the pentacene based thin film transistor was also conducted by transfer length method (TLM) with different annealing temperature in Al- and Ti-pentacene junctions to confirm the Fermi level pinning phenomenon. For Al- and Ti-pentacene junctions, is was found that as the surface quality of the pentacene films changed as annealing temperature increased, the hole-barrier height (h-BH) that were controlled by Fermi level pinning were effectively reduced.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.30 no.9
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• pp.566-571
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• 2017

A soft baking process was used to enhance the electrical characteristics of solution-processed indium-zincoxide (IZO) thin-film transistors (TFTs). We demonstrate a stable soft baking process using a hot plate in air to maintain the electrical stability and improve the electrical performance of IZO TFTs. These oxide transistors exhibited good electrical performance; a field-effect mobility of $7.9cm^2/Vs$, threshold voltage of 1.4 V, sub-threshold slope of 0.5 V/dec, and a current on/off ratio of $2.9{\times}10^7$ were measured. To investigate the static response of our solutionprocessed IZO TFTs, simple resistor load type inverters were fabricated by connecting a resistor (5 or $10M{\Omega}$). Our IZO TFTs, which were manufactured using the soft baking process at a baking temperature of $120^{\circ}C$, performed well at the operating voltage, and are therefore a good candidate for use in advanced logic circuits and transparent display backplanes.

• Journal of the Korean Institute of Telematics and Electronics
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• v.20 no.2
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• pp.7-15
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• 1983

In recent years, the logic circuits of high function have been developed to VLSI by the radical advancement of semi-conductor technologies. Under the above influence, it has become possible to design the special VLSI chips for high speed of numerical value processing, wide-band, image processing, etc. And, the development of the VLSI from various kinds of software package has become quite possible. This paper is to propose the technical skill of hardware design about general software package (BMD). The decrease of speed of former statistics processing caused by depending on software only is improved by hardware. In regard of design algorithm, the main system will be able to be established by considering of special feature of statistics. As a result, the complexity of software package is excluded by hardware. And, the efficiency is improved by high speed processing.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.5
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• pp.2291-2293
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• 2011

In this paper, the composes with digital position with a computer logical operation order with the signal processing method which is pliability and result of the logical operation which confronts in input signal from the outside input-output Channel leads and about the drive which the possibility to output at the outside is a research. This Decoder IC Multiplexer & De-multiplexer, position the function with from the digital signal circle where the imagination embodiments and BIT outputs of IC etc. are possible is possible in basic and usefully from the general industrial, could be used.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.7
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• pp.747-752
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• 2014

This paper relates 10% shrink from $0.13{\mu}m$ design for logic devices as well as input and output (I/O) circuits, different from the previous shrink methodologies which shrink only core device. Thin gate oxide was changed to decoupled plasma nitridation(DPN) oxide as a thin gate oxide (1.2V) to reduce the flicker noise, resulting in three to five times lower flicker noise than pre-shrink process. Unavoidable issue by shrink is capacitor for this normally metal insulator metal (MIM). To solve this issue, 20% higher unit MIM capacitor ($1.2fF/{\mu}m^2$) was developed and its performance were evaluated.