• Progress in Superconductivity
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• v.6 no.1
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• pp.7-12
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• 2004

Due to the very fast switching speed of Josephson junctions, superconductive digital circuit has been a very good candidate fur future electronic devices. High-speed and Low-power microprocessor can be developed with Josephson junctions. As a part of an effort to develop superconductive microprocessor, we have designed an RSFQ 4-bit ALU (Arithmetic Logic Unit) in a pipelined structure. To make the circuit work faster, we used a forward clocking scheme. This required a careful design of timing between clock and data pulses in ALU. The RSFQ 1-bit block of ALU used in this work consisted of three DC current driven SFQ switches and a half-adder. We successfully tested the half adder cell at clock frequency up to 20 GHz. The switches were commutating output ports of the half adder to produce AND, OR, XOR, or ADD functions. For a high-speed test, we attached switches at the input ports to control the high-speed input data by low-frequency pattern generators. The output in this measurement was an eye-diagram. Using this setup, 1-bit block of ALU was successfully tested up to 40 GHz. An RSFQ 4-bit ALU was fabricated and tested. The circuit worked at 5 GHz. The circuit size of the 4-bit ALU was 3 mm ${\times}$ 1.5 mm, fitting in a 5 mm ${\times}$ 5 mm chip.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.811-814
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• 1998

REcent research about current testing($\textrm{I}_{DDQ}$ testing) has been emphasizing that $\textrm{I}_{DDQ}$ testing in addition to the logical voltage testing is necessary to increase the fault coverage. The $\textrm{I}_{DDQ}$. testing can detect physical faults other than the classical stuck-at type fault, which affect reliability. One of the most critical issues in the $\textrm{I}_{DDQ}$ testing is to insert a built-in current sensor (BICS) that can detect abnormal static currents from the power supply or to the ground. This paper presents a new BICS for internal current testing for large CMOS logic circuits. The proposed BICS uses a single phase clock to minimize the hardware overhead. It detects faulty current flowing and converts it into a corresponding logic voltage level to make converts it into a corresponding logic voltage level to make it possible to use the conventional voltage testing techniqeus. By using current mirroring technique, the proposed BICS can work at very high speed. Because the proposed BICS almost does not affects normal operation of CUT(circuit under test), it can be used to a very large circuit without circuit partitioning. By altenating the operational modes, a circuit can be $\textrm{I}_{DDQ}$-tested as a kind of self-testing fashion by using the proposed BICS.

• The Magazine of the IEIE
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• v.25 no.5
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• pp.31-41
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• 1998

With the advent of portable electronic systems, power consumption has recently become a major issue in circuit and system design. Furthermore, the sophisticated fabrication technology makes it possible to embed more functions and features in a VLSI chip, consequently calling for both higher performance and lower power to deal with the ever growing complexity of system algorithms than in the past. VLSI designers should cope with two conflicting constraints, high performance and low power, offering an optimum trade off of these constraints to meet requirements of system. Historically, VLSI designers have focused on performance improvement, and power dissipation was not a design criteria but an afterthought. This design paradigm should be changed, as power is emerging as the most critical design constraint. In VLSI design, low power design can be accomplished through many ways, for instance, process, circuit/logic design, architectural design, and etc.. In this paper, a few low power design examples, which have been used in 8 bit micro-controller core, and can be used also in 4/16/32 bit micro-controller cores, are presented in the areas of circuit, logic and architectural design. We first propose a low power guidelines for micro-controller design in SAMSUNG, and more detailed design examples are followed applying 4 specific design guidelines. The 1st example shows the power reduction through reduction of number of state clocks per instruction. The 2nd example realized the power reduction by applying RISC(Reduced Instruction Set Computer) concept. The 3rd example is to optimize the algorithm for ALU(Arithmetic Logic Unit) to lower the power consumption, Lastly, circuit cells designed for low power are described.

• IEIE Transactions on Smart Processing and Computing
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• v.2 no.4
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• pp.248-254
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• 2013

The size and power consumption of digital circuits including the dimming circuit part will increase for high-performance solid state lighting (SSL) systems in the future. This study examined the low-power consumption of adiabatic dynamic CMOS logic (ADCL) due to the principles of adiabatic charging. Furthermore, the designed low-power ADCL digital pulse width modulation (PWM) was optimized for SSL dimming systems. For this purpose, an ADCL digital 3-bit PWM was optimized in two steps. In the first step, the architecture of the ADCL digital 3-bit PWM was miniaturized. In the second step, the clock cut-off circuit was designed and added to the ADCL PWM. As a result, compared to the original configuration, 60 transistors and 15 capacitors of ADCL digital 3-bit PWM were reduced for miniaturization. Moreover, the clock cut-off circuit, which controls wake-up and sleep mode of ADCL D-FFs, was designed. The power consumption of an optimized ADCL digital PWM for all bit patterns decreased by 54 %.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.778-781
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• 2002

In this paper, we designed the anti-fuse program circuit, and there are an anti-fuse program/sense/latch circuit, a negative voltage generator, power-up circuit and etc. in this circuit. An output voltage of a negative voltage generator is about -4,51V. We detected certainly it regardless of simulation result power rise time or temperature change to detect the anti-fuse program state of an anti-fuse program/sense/latch circuit and were able to know what performed a steady action. And as a result of having done a simulation while will change a resistance value voluntarily in order to check an anti-fuse resistance characteristic of this circuit oneself, it recognized as a programmed anti-fuse until 23k$\Omega$, and we were able to know that this circuit was a lot of margin than general anti-fuse resistance 500$\Omega$. Therefore, the anti-fuse program circuit of this study showed that was able to apply for configuration of the programmable logic device.

• The KIPS Transactions:PartA
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• v.15A no.3
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• pp.135-140
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• 2008

This paper describes a high-speed CMOS demultiplexer using redundant multi-valued logic (RMVL). The proposed circuit receives serial binary data and is converted to parallel redundant multi-valued data using RMVL. The converted data are reconverted to parallel binary data. By the redundant multi-valued data conversion, the RMVL makes it possible to achieve higher operating speeds than that of a conventional binary logic. The implemented demultiplexer consists of eight integrators. Each integrator is composed of an accumulator, a window comparator, a decoder and a D flip flop. The demultiplexer is designed with TSMC $0.18{\mu}m$ standard CMOS process. The validity and effectiveness are verified through the HSPICE simulation. The demultiplexer is achieved the maximum data rate of 20 Gb/s and the average power consumption of 95.85 mW.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.6
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• pp.131-139
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• 1989

This paper proposes Domino CMOS NOR-NOR Array Logic design method which has the same as characteristic of CMOS and Domino CMOS in Array Logic like PLA, good operation feature, high desity, easy test generation. This testable design method can detect all of faults in the circuit using simple additional circuit and solve the parasitic capacitance problem by improving the pull-down characteristics. A Test generation algorithm and test procedure using concept of PLA product term and personality matrix are proposed, and it was implemented in PASCAL language. This design method is verified by SPICE and P-SPICE simulation.

• The Journal of Korean Association of Computer Education
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• v.11 no.1
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• pp.23-32
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• 2008

In this paper, we have investigated the education effect of a web-based virtual laboratory for digital logic circuits which consists of multimedia contents about the usages of equipments for logic circuit experiments and the experimental logic circuits. In case of the engineering experiment of the lower grades in universities, preunderstanding about the usages of experimental equipments and the experimental circuits is necessary for the learners to conduct the experiments well. But it is impossible for the learners to have access to the real experimental equipments earlier due to the lack of equipments and the difficulty in management of the equipments. We have implemented the digital logic circuit virtual laboratory which provides the same experimental environment as a real experimental lab, and the learner can conduct the same experiments as the real ones before the real laboratory class. The learners using the laboratory have reduced the experiment completion time by the average of about 8.2% during a term, compared with the learners not using the lab.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.11
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• pp.12-19
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• 1997

In this paper, we present a logic synthesis algorithm for low powr design fo combinational circuits. The proposed algorithm reduces power dissipation by eliminating unnecessary signal transitions. The proposed algorithm restructures a given circuit by using a kernel as prediction logic in a precomputation-based scheme such that switching activity of circuit can be minimized. Experimental results show that the system is efficient for low power design of combinational circuits.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.19 no.37
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• pp.9-20
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• 1996

The writer has made efforts to solve the weaknesses of the traditional systems through reconstructing cost information systems by introducing 'logical circuit concept' instead of account. As the new designed systems also allow the basic thought of double entry, they are compatiable with the traditional ones. For this, the writer included both monetary and physical information in the systems, replaced the concept of debit & credit with the concept of inputs & outputs, and changed transfer concept between accounts based on reverse logic into flow concept between unit systems based on proceeding logic.