• Journal of the Korea Furniture Society
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• v.27 no.2
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• pp.104-110
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• 2016

The aim of this study is to develop and suggest the handle for lockers according to the design process which are used for keeping of student's personal stuffs such as books, writing implements and gym uniform in elementary, middle and high school and university as well. This includes the design development for ILGUMTUR which is specialized for office furniture, but does not own the intellectual property right yet. The design concept based on the domestic locker market survey is recessed handle at low- to intermediate price and it's material should be plastic what is solid and light. The lock system should be constructed by molding process and the name plate can be exchanged every time the owner of locker changes. Contrary to the right angle of it's external appearance, the handle of the locker is designed to be softly round and the simplicity is pursued for an easy production. On the basis of this design concept the sketch has been drawn and upgraded in full by 3D-rendering. Then the mock-up has been completed by 3D printer and ILGUMTUR has obtained a patent for the locking system based on the rotation of 2 circles.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.3
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• pp.399-405
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• 2011

In this paper, we present the design of Q-band LC VCO and injection locking buffer for 77 GHz automotive radar sensor using 130 nm RF CMOS process. To improve the phase noise characteristic of LC tank, the transmission line is used. The negative resistance by the active device cross-coupled pair of buffer is used for high output power, with or without oscillation of buffer. The measured phase noise is -102 dBc/Hz at 1 MHz offset frequency and tuning range is 34.53~35.07 GHz. The output power is higher than 4.1 dBm over entire tuning range. The fabricated chip size is $510{\times}130\;um^2$. The power consumption of LC VCO is 10.8 mW and injection locking buffer is 50.4 mW from 1.2 V supply.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.411-424
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• 2017

An all-digital delay-locked loop (DLL) for a mobile memory interface, which runs at 0.11-2.5 GHz with a phase-shift capability of $180^{\circ}$, has two internal DLLs: a global DLL which uses a time-to-digital converter to assist fast locking, and shuts down after locking to save power; and a local DLL which uses a phase detector with an adaptive phase sampling window (WPD) to reduce jitter accumulation. The WPD in the local DLL adjusts the width of its sampling window adaptively to control the loop bandwidth, thus reducing jitter induced by UP/DN dithering, input clock jitter, and supply/ground noise. Implemented in a 65 nm CMOS process, the DLL operates over 0.11-2.5 GHz. It locks within 6 clock cycles at 0.11 GHz, and within 17 clock cycles at 2.5 GHz. At 2.5 GHz, the integrated jitter is $954fs_{rms}$, and the long-term jitter is $2.33ps_{rms}/23.10ps_{pp}$. The ratio of the RMS jitter at the output to that at the input is about 1.17 at 2.5 GHz, when the sampling window of the WPD is being adjusted adaptively. The DLL consumes 1.77 mW/GHz and occupies $0.075mm^2$.

• Clinics in Shoulder and Elbow
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• v.17 no.4
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• pp.175-180
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• 2014

Background: For Neer type IIB fracture of distal clavicle with coracoclavicular ligament injury, various surgical treatments have been used in literatures. However, there was no consensus on the optimal treatment. The aim of this study is to report the clinical and radiological results of open reduction and internal fixation of unstable distal clavicle fracture and suture augmentation of disrupted coracoclavicular ligament. Methods: A prospective study was performed in 23 patients with Neer type IIB distal clavicle fracture in Seoul Medical Center, Eulji Hospital, and National Medical Center. Firstly, suture anchors are inserted in the base of coracoid process and preliminary reduction was achieved by tie-off of three suture limbs around the clavicle. Then, the final fixation was completed with anatomical locking plate. Bony union and the distance between coracoclavicular ligaments were evaluated. Clinical results and complications including stiffness and secondary procedures were evaluated. Results: Bony union was achieved in all cases except one (22 of 23). At mean 14.9 months, no significant difference in the mean coracoclavicular distance was observed compared to uninjured shoulder ($8.2{\pm}7.9mm$ versus $7.3{\pm}3.4mm$, p=0.14). Pain visual analogue scale, American Shoulder and Elbow Surgeons score, Constant score, and Disabilities of the Arm, Shoulder and Hand score were 0.5, 83.4, 78.5, and 6.2, respectively. Revision surgery was performed in one case of nonunion. Four patients who complained of skin irritation underwent implant removal. Conclusions: In cases of an unstable distal clavicle fracture with coracoclavicular ligament disruption, satisfactory clinical results were obtained by locking plate fixation and coracoclavicular ligament suture augmentation concurrently.

• Journal of Internet Computing and Services
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• v.12 no.3
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• pp.17-26
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• 2011

We have developed a wearable device that can convert sensor data into real-time step counts. Sensor data on gait were acquired using a triaxial accelerometer. A test was performed according to a test protocol for different walking speeds, e.g., slow walking, walking, fast walking, slow running, running, and fast running. Each test was carried out for 36 min on a treadmill with the participant wearing an Actical device, and the device developed in this study. The signal vector magnitude (SVM) was used to process the X, Y, and Z values output by the triaxial accelerometer into one representative value. In addition, for accurate step-count detection, we used three algorithms: an heuristic algorithm (HA), the adaptive threshold algorithm (ATA), and the adaptive locking period algorithm (ALPA). The recognition rate of our algorithm was 97.34% better than that of the Actical device(91.74%) by 5.6%.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.4
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• pp.37-44
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• 2009

A novel phase-locked loop(PLL) architecture with resistance and capacitance scaling scheme has been proposed. The proposed PLL has three charge pumps. The effective capacitance and resistance of the loop filter can be scaled up/down according to the locking status by controlling the direction and magnitude of each charge pump current. This architecture makes it possible to have a narrow bandwidth and low resistance in the loop filter, which improves phase noise and reference spur characteristics. It has been fabricated with a 3.3V $0.35{\mu}m$ CMOS process. The measured locking time is $25{\mu}s$ with the measured phase noise of -105.37 dBc/Hz @1MHz and the reference spur of -50dBc at 851.2MHz output frequency

• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.8
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• pp.1068-1075
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• 2018

In this paper, a novel PLL has been proposed that reduces the size of the loop filter while suppressing spur by using a VCO with two inputs. Through the stability analysis according to the operating status, the PLL is designed to operate stably after the phase fixing. The capacitor of loop filter usually occupies larger area of PLL. It is a VCO that can reduce the size of the loop filter by increasing the effective capacitance of the capacitor through the simultaneous charge and discharge operation by two charge pumps and has two signals operating in opposite phases. The settling time of set to $80{\mu}s$ approximately by using a LSI(Locking Status Indicator) indicating the phase locking status. The proposed PLL is designed using a supply voltage of 1.8V and a $0.18{\mu}m$ CMOS process.

• The Transactions of the Korea Information Processing Society
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• v.4 no.3
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• pp.639-648
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• 1997

As the areas of computer application are expanded, the real-time applicition enviroments that must process as many transactions as possible within their deadlines have been increased recently. Conventional disk based databaes system is not appropriate in real-time transaction processing due to delying time for disk I/O processing. When the system is overloaede, the performance of transaction scheduling technique using earliest deadline first deteriorates rapidly because it can assign the highest priority ot a transaction that has already missed or is about to miss tis deadline. Therfore, the performance of suggested transaction secheduling technique is made to improved by propos-ing the doule locking mechanism based on priority. Finally, in order to evaluate the performance of the proposed priority-based double locking techniques under single proessor and main memory database system environments, the simulation model was developed using the SLAM II language.

• Korean Journal of Optics and Photonics
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• v.13 no.5
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• pp.384-389
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• 2002

A new idea of the wavelength locking module for DWDM application was investigated in the present research. Only one etalon photo-diode is generally used in the internal/external wavelength locking system. For the internal wavelength locking module with 50 GHz applications, an algle tuning method of the etalon commonly applied. However, the alignment process of the etalon with the angle tuning method is limited because the lock performance is extremely sensitive accoriding to the change of the tilting angle. In an optical viewpoint, the alignment tolerance of the locker module with the etalon PD array block was good, and the precise tuning of the wavelength was possible. The characteristics of free spectral range (FSR) and peak shift of wavelength according to the tilting angle with the locker module was investigated. For the present module, the optimized initial tilting angle was experimentally obtained.

• Journal of IKEEE
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• v.23 no.3
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• pp.800-804
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• 2019

This paper presents a dual-loop sub-sampling digital PLL for a 2.4 GHz IoT applications. The PLL initially performs a divider-based coarse lock and switches to a divider-less fine sub-sampling lock. It achieves a low in-band phase noise performance by enabling the use of a high resolution time-to-digital converter (TDC) and a digital-to-time converter (DTC) in a selected timing range. To remove the difference between the phase offsets of the coarse and fine loops, a phase offset calibration scheme is proposed. The phase offset of the fine loop is estimated during the coarse lock and reflected in the coarse lock process, resulting in a smooth transition to the fine lock with a stable fast settling. The proposed digital PLL is designed by SystemVerilog modeling and Verilog-HDL and fully verified with simulations.