• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2004.05a
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• pp.28-31
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• 2004

A Quadrature phase detector for high-speed delay-locked loop is introduced. The proposed Quadrature phase detector is composed of two nor gates and it determines if the phase difference of two input clocks is 90 degrees or not. The delay locked loop circuit including the Quadrature phase detector is fabricated in a 0.18 urn standard CMOS process and it operates at 5 ㎓ frequency. The phase error of the delay-locked loop is maximum 2 degrees and the circuits are robust with voltage, temperature variations.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.1 s.92
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• pp.49-55
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• 2005

In this paper, the phase locked harmonic oscillator(PLHO) using the analog PLL(Phase Locked Loop) is designed and implemented for a wireless LAN system. The harmonic oscillator is consisted of a ring resonator, a varactor diode and a PLL circuit. Because the fundamental fiequency of 8.5 GHz is used as the feedback signal for the PLL and the 2nd harmonic of 17.0 GHz is used as the output, a analog frequency divider for the phase comparison in the PLL system can be omitted. For the simple PLL circuit, the SPD(Sampling Phase Detector) as a phase comparator is used. The output power of the phase locked harmonic oscillator is 2.23 dBm at 17 GHz. The fundamental and 3rd harmonic suppressions are -31.5 dBc and -29.0 dBc, respectively. The measured phase noise characteristics are -87.6 dBc/Hz and -95.4 dBc/Hz at the of offset frequency of 1 kHz and 10 kHz from the carrier, respectively.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.5
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• pp.522-527
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• 2011

In this work, a 54 GHz divide-by-3 injection-locked frequency divider(ILFD) based on ring oscillator has been developed in a 0.13-${\mu}M$ Si RFCMOS technology for phase-locked loop(PLL) application. The free-running frequency is 18.92~19.31 GHz with tuning range of 0~1.8 V, consuming 70 mW with a 1.8 V supply voltage. At 0 dBm input power, the locking range is 1.02 GHz(54.82~55.84 GHz) and, with varactor tuning of 0~1.8 V, the total operating range is 2.4 GHz(54.82~57.17 GHz). The fabricated circuit size is 0.42 mm${\times}$0.6 mm including probing pads and 0.099 mm${\times}$0.056 mm for core area.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.82-87
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• 2008

This paper presents a new fast locking dual-slope phase-locked loop. The conventional dual-slope phase-locked loop consists of two charge pumps and two phase-frequency detectors. In this paper, the dual-slope phase-locked loop was achieved with a charge pump and a phase-frequency detector as adjusting a current of the charge pump according to the phase difference. The proposed circuit was verified by HSPICE simulation with a $0.35{\mu}m$ CMOS standard process parameter. The phase locking time of the proposed dual-slope phase-locked loop was $2.2{\mu}s$ and that of the single-slope phase-locke loop was $7{\mu}s$.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.520-523
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• 2004

A phase-locked loop control system designed by using the linear quadratic regulator approach is presented in this paper. The system thus designed is optimal system when system is in locked state and the parameter value of loop filter which is an active PI filter can be obtained easily. By considering the structure of loop filter of phase-locked loop is included in the process to be controlled, a type 1 servo system can be constructed when voltage control oscillator is considered as an integrator. The integral gain of the proposed system obtained by linear quadratic regulator approach can be used as an optimal value to design the parameter of loop filter. The implemented result in controlling the second-order lag pressure process by using the proposed scheme show that the system response is fast with no overshoot and no steady-state error. Furthermore, the experimental results are also shown in term of output disturbance effect rejection, tracking and process parameter changed.

• ETRI Journal
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• v.34 no.2
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• pp.175-183
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• 2012

Conventional synchronization algorithms for impulse radio require high-speed sampling and a precise local clock. Here, a phase-locked loop (PLL) scheme is introduced to acquire and track periodical impulses. The proposed impulse PLL (iPLL) is analyzed under an ideal Gaussian noise channel and multipath environment. The timing synchronization can be recovered directly from the locked frequency and phase. To make full use of the high harmonics of the received impulses efficiently in synchronization, the switching phase detector is applied in iPLL. It is capable of obtaining higher loop gain without a rise in timing errors. In different environments, simulations verify our analysis and show about one-tenth of the root mean square errors of conventional impulse synchronizations. The developed iPLL prototype applied in a high-speed ultra-wideband transceiver shows its feasibility, low complexity, and high precision.

• Journal of Physiology & Pathology in Korean Medicine
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• v.21 no.4
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• pp.795-802
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• 2007

The fire not to back to its origin(火不歸原) is said that source yang(元陽) of sea of qi(氣海) rises because fire(火) of lower energizer(下焦) can't return to its origin. Successive medical men regarded the cause of it as yang deficiency(陽虛) or yin deficiency(陰虛) generally, but Jangseoksun(張錫純) presented eight kinds of cause, they are syndrome of upcast yang(戴陽證), deficiency of qi(氣虛), yin deficiency, yin and yang deficiency(陰陽虛), thoroughfare qi ascending counterflow(衝氣上衝), heart fire(心火), yang deficiency with cold fluid retention(寒飮) in middle energizer(中焦寒飮), yang deficiency with sunken cold locked in(沈寒錮冷). The method of conducting fire back to its origin may be the treatment of fire not to back to its origin as an interpretation of the phrase in a broad sense, but it is limited to yang deficiency with sunken cold locked in besides syndrome of upcast yang as the treatment based on pathological conditions. By this standpoint Eunsuryong(殷壽龍) used conducting fire back to its origin to remove hidden cold(伏寒) and make rising false fire(假火) settle. The meaning of conducting fire back to its origin is not just raise yang qi(陽氣) but break sunken cold locked in by using the drugs like Buja(附子), Yukgye(肉桂). Jakyak(芍藥) can concentrate yang qi on the life gate(命門) by converging it, Sukjihwang(熟地黃) can supply yin essence(陰精) and check the intense nature of tonifing yang(補陽) drugs. So if we want to use the method of conducting fire back to its origin, we should confirm the symptoms of sunken cold locked in and yang deficiency not to misdiagnose yin deficiency.

• Structural Engineering and Mechanics
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• v.44 no.6
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• pp.763-774
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• 2012

Reinforced concrete frame structures with masonry infill walls constitute the significant portion of the building stock in Turkey. Therefore it is very important to understand the behavior of masonry infill frame structures under earthquake loads. This study presents an experimental work performed on reinforced concrete (RC) frames with different types of masonry infills, namely standard and locked bricks. Earthquake effects are induced on the RC frames by quasi-static tests. Results obtained from different frames are compared with each other through various stiffness, strength, and energy related parameters. It is shown that locked bricks may prove useful in decreasing the problems related to horizontal and vertical irregularities defined in building codes. Moreover tests show that locked brick infills maintain their integrity up to very high drift levels, showing that they may have a potential in reducing injuries and fatalities related to falling hazards during severe ground shakings.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.5
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• pp.949-954
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• 2007

In this work, temperature stable frequency-to-voltage converter is proposed. In FVC circuit input frequency is converted into output voltage signal. A FLL is similar to PLL in the way that it generates an output signal which tracks an input reference signal. A PLL is built on a phase detector, a charge pump, and a low pass filter. However, FLL does not require the use of the phase detector, the charge pump and low pass filter. The FVC is designed by using $0.25{\mu}m$ CMOS process technology. From simulation results, the variation of output voltage is less than ${\pm}2%$ in the temperature range $0^{\circ}C\;to\;75^{\circ}C$ when the input frequency is from 70MHz to 140MHz.

• Fire Science and Engineering
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• v.34 no.2
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• pp.64-71
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• 2020

In this paper, the fire risk of a single-phase induction motor under a locked-rotor condition is described. In general, motor failure occurs in the locked-rotor condition owing to poor rotation of the rotor. Large inrush current flows when a motor starts, which is approximately 2-15 times larger than the rated current. In a single-phase induction motor under the locked-rotor condition, a large current that corresponds to the inrush current flows continuously through the stator winding. Such an overcurrent rises the temperature inside the stator winding, and thus the insulating material may catch fire. In this study, the restrained operating condition of the single-phase induction motor was simulated. Further, the degree of the overcurrent and temperature rise in the stator winding was measured. The experimental results, confirmed that the overcurrent was seven times larger than the rated current and the fire commenced at a temperature of approximately 300 ℃ inside the stator winding.