• Title/Summary/Keyword: Lock-In

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Infulence of doppler effects on the tracking performance of a dely locked loop (도플러 효과에 의한 지연 동기 루프의 추적 성능분석)

  • 임성준;유흥균
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.23 no.4
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    • pp.857-864
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    • 1998
  • The infuluence of Doppler effects on the tracking performance of a noncoherent second-order delay locked loop (DLL) operating on a data modulated signal is investigated. For the perfoermance analysis we consider the tracking accuracy (steady state error and jitter) of the linear DLL and the reliability of the nonlinear loop. The nonlinear analysis concerning the loop reliability makes use of an asympototic expansion for the MTLL(mean time to lose lock) which has been derived by applying the singular perturbation method. In particular, we give optimal loop parameters and the optimal bandwidth of the bandpass filter in the loop arms to achieve a maximum MTLL. Since Doppler effects can be producesd comparatively in LEO system, we can espect the more reliable DLL loop design. by using the results of the circuit simulation, the delay lock loop is synthesized in FPGA, and verified to get the GPS data from the STR-2770 GPS simulator system. So, the synthesized logic circuit is shown be accurately performed.

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A PLL Based 32MHz~1GHz Wide Band Clock Generator Circuit for High Speed Microprocessors (PLL을 이용한 고속 마이크로프로세서용 32MHz~1GHz 광대역 클럭발생회로)

  • Kim, Sang-Kyu;Lee, Jae-Hyung;Lee, Soo-Hyung;Chung, Kang-Min
    • The Transactions of the Korea Information Processing Society
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    • v.7 no.1
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    • pp.235-244
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    • 2000
  • This paper presents a low power PLL based clock geneator circuit for microprocessors. It generates 32MHz${\sim}$1GHz clocks and can be integrated inside microprocessor chips. A high speed D Flip-Flop is designed using dynamic differential latch and a new Phase Frequency Detector(PFD) based on this FF is presented. The PFD enjoys low error characteristics in phase sensitivity and the PLL using this PFD has a low phase error. To improve the linearity of voltage controlled oscillator(VCO) in PLL, the voltage to current converter and current controlled oscillator combination is suggested. The resulting PLL provides wide lock range and extends frequency of generated clocks over 1 GHz. The clock generator is designed by using $0.65\;{\mu}m$ CMOS full custom technology and operates with $11\;{\mu}s$ lock-in time. The power consumption is less than 20mW.

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Concurrency Control with Dynamic Adjustment of Serialization Order in Multilevel Secure DBMS (다단계 보안 데이타베이스에서 직렬화 순서의 동적 재조정을 사용한 병행수행 제어 기법)

  • Kim, Myung-Eun;Park, Seok
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.9 no.1
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    • pp.15-28
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    • 1999
  • In Multilevel Secure Database Management System(MLS/DBMS), we assume that system has a security clearance level for each user and a classification level for each data item in system and the objective of these systems is to protect secure information from unauthorized user. Many algorithms which have been researched have focus on removing covert channel by modifying conventional lock-based algorithm or timestamp-based algorithm. but there is high-level starvation problem that high level transaction is aborted by low level transaction repeatedly. In order to solve this problem, we propose an algorithm to reduce high-level starvation using dynamic adjustment of serialization order, which is basically using orange lock. Because our algorithm is based on a single version unlike conventional secure algorithms which are performed on multiversion, it can get high degree of concurrency control. we also show that it guarantees the serializability of concurrent execution, and satisfies secure properties of MLS/DBMS.

Side-Channel Attack of Android Pattern Screen Lock Exploiting Cache-Coherent Interface in ARM Processors (ARM 캐시 일관성 인터페이스를 이용한 안드로이드 OS의 스크린 잠금 기능 부채널 공격)

  • Kim, Youngpil;Lee, Kyungwoon;Yoo, Seehwan;Yoo, Chuck
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.32 no.2
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    • pp.227-242
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    • 2022
  • This paper presents a Cache-Coherency Interconnect(CCI)-based Android pattern screen lock(PSL) attack on modern ARM processors. CCI has been introduced to maintain the cache coherency between the big core cluster and the little core cluster. That is, CCI is the central interconnect inside SoC that maintains cache coherency and shares data. In this paper, we reveal that CCI can be a side channel in security, that an adversary can observe security-sensitive operations. We design and implement a technique to compromise Android PSL within only a few attempts using the information of CCI in user-level applications on Android Nougat. Further, we analyzed the relationship between the pattern complexity and security. Our evaluation results show that complex and simple patterns would have similar security strengths against the proposed technique.

Secure PIN Authentication Technique in Door-Lock Method to Prevent Illegal Intrusion into Private Areas (사적 영역에 불법 침입 방지를 위한 도어락 방식의 안전한 PIN 인증 기법)

  • Hyung-Jin Mun
    • Journal of Practical Engineering Education
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    • v.16 no.3_spc
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    • pp.327-332
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    • 2024
  • The spread of smart phones provides users with a variety of services, making their lives more convenient. In particular, financial transactions can be easily made online after user authentication using a smart phone. Users easily access the service by authenticating using a PIN, but this makes them vulnerable to social engineering attacks such as spying or recording. We aim to increase security against social engineering attacks by applying the authentication method including imaginary numbers when entering a password at the door lock to smart phones. Door locks perform PIN authentication within the terminal, but in smart phones, PIN authentication is handled by the server, so there is a problem in transmitting PIN information safely. Through the proposed technique, multiple PINs containing imaginary numbers are generated and transmitted as processed values such as hash values, thereby ensuring the stability of transmission and enabling safe user authentication through a technique that allows the PIN to be entered without exposure.

A Kinematic Analysis of the Defence Types during Body Lock Technique in the Ground Wrestling (그라운드 레슬링 가로들기 공격 시 수비 유형의 운동학적 분석)

  • Hah, Chong-Ku;Ryu, Ji-Seon
    • Korean Journal of Applied Biomechanics
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    • v.17 no.1
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    • pp.155-164
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    • 2007
  • This study is to find out effective defensive type by analysis on differences among three different defence types of the body lock technique in the ground wrestling. The subjects are 5 athletes who are in 60kg weight class. To get the kinematic analysis seven ProReflex MCU-240(Motion Capture Unit), infrared rays cameras, which was produced by Qualisys, were used to get a two-dimensional coordinate. Following are the analysis result from kinematic factors such as time element, speed element and angular element. 1. During position of ground wrestling, the average necessary time until defender's hip joint touches the mat for Phase1 was $0.34{\pm}0.14sec$ at side position was the shortest space of time out of three types, and Phase2 was $0.21{\pm}0.02sec$ at front position was the shortest space of time out of three types. Moreover, side defence position was the shortest for total average necessary time with $0.78{\pm}0.05sec$. 2. The movement change for hip joint was $57.21{\pm}20.17cm$ for front, $43.35{\pm}7.13cm$ for rear, and $18.67{\pm}10.24cm$ for side at Phase1 and $42.08{\pm}17.56cm$ for side, $16.61{\pm}6.34cm$ for front, and $1.48{\pm}1.29cm$ for rear at Phase2. 3. Movement speed of hip joint at defensive type were most effective in success and fail rate at Phase 1 and its frontal average speed was fastest with $1.01{\pm}0.23m/s$ following by $0.52{\pm}0.15m/s$ for side, and $0.62{\pm}0.15m/s$ for rear. The average for total change of speed is $0.79{\pm}0.32m/s$ for front, $0.78{\pm}0.17m/s$ for side, and $0.49{\pm}0.08m/s$ for rear. 4. The joint angle gets smaller in a order by rear, front, and side for the size of hip joint angle and knee angle for different defensive type. 5. As a result of one-way ANOVA on linear velocity for hip joint in frontal defence(phase1) was significance ($\alpha$=.05), but phase 2 was not significance. Synthetically, analyzing on differences among three different defence types which were front, rear, and side of the body lock technique in the ground wrestling, front defensive type was the most effective. In future, there should be more studies regarding on defence at not a laboratory study but a field study to help out wrestler to pertinent techniques to improve the game of wrestling.

A Compensation Method of Timing Signals for Communications Networks Synchronization by using Loran Signals (Loran 신호 이용 통신망 동기를 위한 타이밍 신호 보상 방안)

  • Lee, Young-Kyu;Lee, Chang-Bok;Yang, Sung-Hoon;Lee, Jong-Gu;Kong, Hyun-Dong
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.34 no.11A
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    • pp.882-890
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    • 2009
  • In this paper, we describe a compensation method that can be used for the situation where Loran receivers lose their phase lock to the received Loran signals when Loran signals are employed for the synchronization of national infrastructures such as telecommunication networks, electric power distribution and so on. In losing the phase lock to the received signals in a Loran receiver, the inner oscillator of the receiver starts free-running and the performance of the timing synchronization signals which are locked to the oscillator's phase is very severly degraded, so the timing accuracy under 1 us for a Primary Reference Clock (PRC) required in the International Telecommunications Union (ITU) G.811 standard can not be satisfied in the situation. Therefore, in this paper, we propose a method which can compensate the phase jump by using a compensation algorithm when a Loran receiver loses its phase lock and the performance evaluation of the proposed algorithm is achieved by the Maximum Time Interval Error (MTIE) of the measured data. From the performance evaluation results, it is observed that the requirement under 1 us for a PRC can be easily achieved by using the proposed algorithm showing about 0.6 us with under 30 minutes mean interval of smoothing with 1 hour period when the loss of phase lock occurs.

Concurrency Control and Consistency Maintenance of Cached Spatial Data in Client-Server Environment (클라이언트-서버 환경에서 캐쉬된 공간 데이터의 동시성 제어 및 일관성 유지 기법)

  • Shin, Young-Sang;Hong, Bong-Hee
    • Journal of KIISE:Databases
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    • v.28 no.3
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    • pp.512-527
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    • 2001
  • In a client-server spatial database, it is desirable to maintain the cached data in a client side to minimize the communication overhead across a network. This paper deals with the issues of concurrency and consistency of map updates in this environment. A client transaction to update map data is an interactive work and takes a long time to complete it. The map update in a client site may affect the other sites'updates because of dependencies between spatial data stored at different sites. The concurrent updates should be propagated to the other clients as well as the server to keep the consistency of map replicated in a client cache, and also the communication overhead of the update propagation should be minimized not to lose the benefit of caching. The newly proposed cache region locking with CR lock and CX lock controls the update dependency due to spatial relationships. CS lock and COD lock are suggested to use optimistic detection-based approaches for guaranteeing the consistency of cached client data. The cooperative update protocol uses these extended locking primitives and Spatial Relationship-based 2PC (SR-based 2PC). This paper argues that the concurrent updates of cached client spatial data can be achieved by deciding on collaborative updates or independent updates based on spatial relationships.

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Synchronization Technique Based on Adaptive Combining of Sub-correlations of Multiband Sine Phased BOC Signals (부상관함수의 적응적 결합에 기반한 다중 대역 Sine 위상 BOC 신호 동기화 기법)

  • Park, Jong-In;Lee, Young-Po;Yoon, Seok-Ho;Kim, Sun-Yong;Lee, Ye-Hoon
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.36 no.11C
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    • pp.694-701
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    • 2011
  • This paper addresses a synchronization technique based on an adaptive combining of the sub-correlation functions obtained from multiband sine phased binary offset carrier (BOC) signals, allowing a BOC signal receiver to deal with multiband sine phased BOC signals. Specifically, we first obtain the sub-correlation functions composing the BOC autocorrelation function, and then, re-combine the sub-correlation functions generating a correlation function with no side-peak. Finally, by replacing the BOC autocorrelation with the correlation function with no side-peak in the delay lock loop, the proposed scheme performs unambiguous signal tracking. The proposed synchronization scheme is applicable to generic sine phased BOC signals. Numerical results demonstrate that the proposed scheme provides a performance improvement over the conventional unambiguous schemes in terms of the tracking error standard deviation.

Concurrency Control and Recovery Methods for Multi-Dimensional Index Structures (다차원 색인구조를 위한 동시성제어 기법 및 회복기법)

  • Song, Seok-Il;Yoo, Jae-Soo
    • The KIPS Transactions:PartD
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    • v.10D no.2
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    • pp.195-210
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    • 2003
  • In this paper, we propose an enhanced concurrency control algorithm that maximizes the concurrency of multi-dimensional index structures. The factors that deteriorate the concurrency of index structures are node splits and minimum bounding region (MBR) updates in multi-dimensional index structures. The proposed concurrency control algorithm introduces PLC(Partial Lock Coupling) technique to avoid lock coupling during MBR updates. Also, a new MBR update method that allows searchers to access nodes where MBR updates are being performed is proposed. To reduce the performance degradation by node splits the proposed algorithm holds exclusive latches not during whole split time but only during physical node split time that occupies the small part of a whole split process. For performance evaluation, we implement the proposed concurrency control algorithm and one of the existing link technique-based algorithms on MIDAS-3 that is a storage system of a BADA-4 DBMS. We show through various experiments that our proposed algorithm outperforms the existing algorithm in terms of throughput and response time. Also, we propose a recovery protocol for our proposed concurrency control algorithm. The recovery protocol is designed to assure high concurrency and fast recovery.