• Journal of KIISE:Computer Systems and Theory
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• v.32 no.2
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• pp.55-67
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• 2005

Separation between computation and communication in system design allows the system designer to explore the communication architecture independently of component selection and mapping. In this paper we present an iterative two-step exploration methodology for bus-based on-chip communication architecture and memory allocation, assuming that memory traces from the processing elements are given from the mapping stage. The proposed method uses a static performance estimation technique to reduce the large design space drastically and quickly, and applies a trace-driven simulation technique to the reduced set of design candidates for accurate Performance estimation. Since local memory traffics as well as shared memory traffics are involved in bus contention, memory allocation is considered as an important axis of the design space in our technique. The viability and efficiency of the proposed methodology arc validated by two real -life examples, 4-channel digital video recorder (DVR) and an equalizer for OFDM DVB-T receiver.

• Korean Journal of Adult Nursing
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• v.24 no.4
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• pp.398-405
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• 2012

Purpose: The purpose of this study was to develop spaced retrieval training as a nursing intervention for patients having an mild alzheimer's disease and to determine the effects of the program on their memory and cognitive function across training sessions. Methods: A non-equivalent control group pre test-post test design was used in this study. Participants were recruited from a local community: 14 patients were allocated into experimental group and 12 patients were allocated into control group. The experimental group was asked to participate in spaced retrieval training over 4 weeks, with seven times a week and 1 hour a session based. The study was conducted from June 20, 2011 to July 17, 2011. Data was analyzed with descriptive statistics, $x^2$-test and t-test using the SPSS/WIN 19.0 program. Results: After spaced retrieval training, the experimental group showed significant increases in scores for memory (t=12.40, p<.001) and cognitive function (t=7.69, p<.001) in comparison to the control group. Conclusion: Spaced retrieval training was effective in increasing cognitive function and memory of patients having mild alzheimer's disease. Therefore spaced retrieval training could be benefit the mild alzheimer's disease.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.1
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• pp.45-51
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• 2004

We have proposed a new shallow trench isolation (STI) process using flowable oxide (F-oxide) chemical vapor deposition (CVD) for DRAM application and it was successfully developed. The combination of F-oxide CVD and HDP CVD is thought to be the superior STI gap-filling process for next generation DRAM fabrication because F-oxide not only improves STI gap-filling capability, but also the reduced local stress by F-oxide in narrow trenches leads to decrease in junction leakage and gate induced drain leakage (GIDL) current. Finally, this process increased data retention time of DRAM compared to HDP STI. However, a serious failure occurred by symphonizing its structural dependency of deposited thickness with poor resistance against HF chemicals. It could be suppressed by reducing the flow time during F-oxide deposition. It was investigated collectively in terms of device yield. In conclusion, the combination of F-oxide and HDP oxide is the very promising technology for STI gap filling process of sub-100nm DRAM technology.

• Journal of electromagnetic engineering and science
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• v.11 no.3
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• pp.213-219
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• 2011

Simulative target generators are needed for testing and calibrating various radar systems. The generator in this study discriminates the transmitting frequency from a radar and simulates parameters like target range, range rate, and atmospheric attenuation using the digital RF memory technique. The simulative target echo is then sent to the radar for testing and evaluation. This paper proposes a novel architecture for controlling the digital RF memory so it continually writes ADC data to the memory and reads it for the DAC with increasing one step address in order to control the delay of target range in a simple way. The target echo is programmed according to various preprogrammed scenarios and is generated in real time using a wireless local area network (LAN). To analyze the detected and generated target information easily, the system times for the radar and simulative target generator are synchronized using a global positioning system (GPS).

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.507-511
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• 2010

Digital Radio Frequency Memory (below, DRFM) performs RF signal data store, delay and re-transmission. DRFM is wildly used as core module of Jammer, EW simulator, Target Echo Generator etc. This paper suggests a hardware design of DRFM which is composed RF section(RF Input/Output Module, Local Oscillator Module) and Digital section(ADC module, memory, DAC module), and confirm the validity of the propose by the test result.

• Journal of Korean Library and Information Science Society
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• v.43 no.2
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• pp.343-364
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• 2012

To examine the locality of Busan is a precondition of examining documenting localities of Busan. What is the locality of Busan and how can I explore the locality of Busan? These are the research questions of this thesis. Memory is fundamental in making an identity. So local memory is fundamental in making locality. Understanding relations between memory and identity, the author explored the locality of Busan by analyzing memories of Busan. To analyze memories of Busan is to examine historical figures of Busan and Cultural Properties of Busan which are on the website of Busan metropolitan city. The results are as follows : According to the analysis of historical figures of Busan, there are no confucius scholars who came from Busan. However in the age of civilization, Busan has produced some talented people by way of receiving a modern education. According to the analysis of Cultural Properties of Busan, Jung-gu(中區) and Seo-gu(西區) and Yeongdo-gu(影島區) are the spaces of migration. Dongnae-gu(東萊區), Suyeong-gu(水營區) and Saha-gu(沙下區) and Gijang-gun(機張郡) are the spaces of settlement. Dong-gu(東區) has changed from a space of settlement into a space of migration with the opening of the Busan Port as a momentum in 1876.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.5
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• pp.83-93
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• 2013

Recently, the SURF algorithm, which is conjugated for object tracking system as part of many computer vision applications, is a well-known scale- and rotation-invariant feature detection algorithm. The SURF, due to its high computational complexity, there is essential to develop a hardware accelerator in order to be used on an IP in embedded environment. However, the SURF requires a huge local memory, causing many problems that increase the chip size and decrease the value of IP in ASIC and SoC system design. In this paper, we proposed a way to design a SURF algorithm in hardware with greatly reduced local memory by partitioning the algorithms into several Sub-IPs using external memory and a DMA. To justify validity of the proposed method, we developed an example of simplified object tracking algorithm. The execution speed of the hardware IP was about 31 frame/sec, the logic size was about 74Kgate in the 30nm technology with 81Kbytes local memory in the embedded system platform consisting of ARM Cortex-M0 processor, AMBA bus(AHB-lite and APB), DMA and a SDRAM controller. Hence, it can be used to the hardware IP of SoC Chip. If the image processing algorithm akin to SURF is applied to the method proposed in this paper, it is expected that it can implement an efficient hardware design for target application.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.06a
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• pp.812-815
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• 2005

The incremental forming process employs several tens or hundreds of continuous local strokes, so the entire process is difficult to analyze due to much computation time and large computer memory. The objective of this work is to propose a new numerical scheme of the finite element method, automatic expansion of domain (AED), and to reduce computation time and computer memory. In the AED scheme, an effective analysis domain in each local forming step is defined and then the domain is automatically expanded in accordance with the repeated process. In order to verify the validity of the criterion for the AED scheme and the applicability of the AED scheme, two-dimensional incremental plane-strain forging process is first analyzed using the proposed scheme with various criteria and full domain. In addition, three-dimensional incremental radial forging process is analyzed to verify the applicability of the proposed scheme to a practical incremental forging process.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.13 no.11
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• pp.5580-5593
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• 2019

A malicious Uniform Resource Locator (URL) recognition and detection method based on the combination of Attention mechanism with Convolutional Neural Network and Long Short-Term Memory Network (Attention-Based CNN-LSTM), is proposed. Firstly, the WHOIS check method is used to extract and filter features, including the URL texture information, the URL string statistical information of attributes and the WHOIS information, and the features are subsequently encoded and pre-processed followed by inputting them to the constructed Convolutional Neural Network (CNN) convolution layer to extract local features. Secondly, in accordance with the weights from the Attention mechanism, the generated local features are input into the Long-Short Term Memory (LSTM) model, and subsequently pooled to calculate the global features of the URLs. Finally, the URLs are detected and classified by the SoftMax function using global features. The results demonstrate that compared with the existing methods, the Attention-based CNN-LSTM mechanism has higher accuracy for malicious URL detection.

• Journal of Electrical Engineering and information Science
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• v.2 no.3
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• pp.105-112
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• 1997

The performance of a shared memory multiprocessor system is very sensitive to process scheduling. w can enhance the performance of a whole system as well as of an individual process by taking the multiprocessor characteristics into account in the design of the process scheduler. In this paper, we proposed a general purpose scheduler for a shared memory multiprocessor, called the Two-Level Multi-Scan (TLMS) process scheduler, that considers the processor affinity loosely and decreases the interference among multiple processors greatly. The TLMS scheduler is composed of a local scheduler at each processor and a semi-global scheduler that balances the load among processors. In particular, the semi-global scheduler tries to minimize priority inversion, which is an important factor of the system performance. The TLMS scheduler also tries to reduce the number of resources to be shared and improves the processor utilization. to meet these requirements, th semi-global scheduler interacts with the operation of the local scheduler when a need arises, thus the name is loose processor-affinity. We also show that the proposed scheduling technique can be extended for other types of resources making it a general purpose resource management queue.