• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.21 no.2
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• pp.94-98
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• 2007

The fault current limiting characteristics of a flux-lock type superconducting fault current limiter (SFCL) considering hysteresis characteristics of a flux-lock reactor, which is an essential component of the flux-lock type SFCL, were investigated. In the normal state, the hysteresis loss of iron core in the flux-lock type SFCL does not happen due to its winding's structure. From the equivalent circuit for the flux-lock type SFCL and the fault current limiting experiments, the hysteresis curves could be drawn. Through the hysteresis curves together with the fault current level due to the inductance ratio between the primary and the secondary windings, the increase of the number of turns in the secondary winding of the flux-lock type SFCL made the fault current level increase. On the other hand, the saturation of iron core was prevented.

• 한국초전도학회:학술대회논문집
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• v.14
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• pp.53-53
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• 2004

• Proceedings of the KIEE Conference
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• 1993.07b
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• pp.1153-1155
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• 1993

This paper presents some experimental result of current limiting, fusing and short circuit interruption behavior by notch construction of thin copper film $35{\mu}m$ on epoxy substrate. A fuse-link having elements of copper film provided high-precision small holes by photo eatching process.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2004.11a
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• pp.121-127
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• 2004

Electric ballast is widely used to turn on the fluorescent. Electric ballast measure occurrence of harmonic through the actual measurement and it is simulated by modeling equivalent circuit for harmonic analysis. The purpose of this paper is to give an equivalent circuit modeling methodology for the harmonic currents generated by single-phase personal computer loads to evaluate a commercially available series resonant filter for the harmonic currents compensation based on the IEC std 61000-3-2 and IEEE 519 standards for limiting harmonic distortion.

• Proceedings of the KIPE Conference
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• 2008.06a
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• pp.520-522
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• 2008

A novel two-switch active clamp forward converter suitable for high input voltage applications is proposed. The main advantage of the proposed converter, compared to the conventional active forward converters, is that circuit complexity is reduced and the voltage stress of the main switches is effectively clamped to either the input voltage or the clamping capacitor voltage by two clamping diodes without limiting the maximum duty ratio. Also, the clamping circuit does not include additional active switches, so a low cost can be achieved without degrading the efficiency. Therefore, the proposed converter can feature high efficiency and low cost for high input voltage applications. The operational principles, features, and design considerations of the proposed converter are presented in this paper. The validity of this study is confirmed by the experimental results from a prototype with 200W, 375V input, and 12V output.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1993.11a
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• pp.35-38
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• 1993

SCLD(supercondocting current 1imiting device) with YBaCuO superconductor was fabricated by the sol-gel and the doctor-blade method. Critical current density ($J_{c}$) and critical current ($I_{c}$) of the SCLD are 100.27 A/$cm^2$and 1A at 77K and the electrodes contact with SCLD by silver paste. The SCL was connected with test circuit in series. When apple iud current exceed critical current value of the SCLD in testing circuit, the SCLD ristricts the over current by generating resistance itself without delay. Resistance of SCLD increase lineary 0 to 1.6$\Omega$ in propotion to applied current above the critical current $I_{c}$.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.823-826
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• 2003

FPGA-based logic emulator with lane gate capacity generally comprises a large number of FPGAs connected in mesh or crossbar topology. However, gate utilization of FPGAs and speed of emulation are limited by the number of signal pins among FPGAs and the interconnection architecture of the logic emulator. The time-multiplexing of interconnection wires is required for multi-FPGA system incorporating several state-of-the-art FPGAs. This paper proposes a circuit partitioning algorithm called SCATOMi(SCheduling driven Algorithm for TOMi)for multi-FPGA system incorporating four to eight FPGAs where FPGAs are interconnected through TOMi(Time-multiplexed, Off-chip, Multicasting interconnection). SCATOMi improves the performance of TOMi architecture by limiting the number of inter-FPGA signal transfers on the critical path and considering the scheduling of inter-FPGA signal transfers. The performance of the partitioning result of SCATOMi is 5.5 times faster than traditional partitioning algorithms. Architecture comparison show that the pin count is reduced to 15.2%-81.3% while the critical path delay is reduced to 46.1%-67.6% compared to traditional architectures.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.29 no.5
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• pp.289-293
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• 2016

The flux-lock type superconducting fault current limiter (SFCL) connects the two parallel windings in parallel with a ferromagnetic core. We suggest that the double quench flux-lock type SFCL should add a third winding. We analyzed characteristics of the fault current and the peak current using the quench of the high-Tc superconducting element. The proposed SFCL's inductances of a primary winding and the third winding were fixed and the amplitude of inductance of the secondary winding was changed. We found that the fault current can be more effectively controlled through the analysis of the equivalent circuit and the short-circuit tests.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.6
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• pp.467-474
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• 1990

In this paper, the circuit that has characteristics of high speed and low dissipation is described. A 4:1 parallel ADC is constructed by using the designed SCFL(Source Coupled FET Logic). The results of simulation shows that comparators is obtained integrated nonlinearity, $\pm$28mV, compared with limiting value, $\pm$68mV, at 66NHz input signal and 2Gs/s Niquist rates and this paper describes low power dissipation about 0.43W by reducing the elements in a ADC design.

• Progress in Superconductivity and Cryogenics
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• v.1 no.1
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• pp.28-32
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• 1999

We have performed an EMTDC simulation for the current limiting effects of a superconducting fault current limiter (SFCL). The fault currents in the 154 kV transmission line between the arbitrary S1 and S2 substations increased up to 54 KA and 60 KA during the line-to-line and three phase faults, respectively. The SFCL with 100$\omega$ of resistance after quench limited the currents to less than 17 KA within a half cycle. This limited current is well below the upper limit of a circuit breaker, suggesting that the resistance of the SFCL in the transmission line is sufficient.