• The Transactions of the Korean Institute of Electrical Engineers D
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• v.55 no.5
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• pp.229-235
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• 2006

High speed PC-based DIO(Digital I/O) system that consists of a master device and slave I/O devices is developed. The PCI interfaced master device controls all of serial communications, reducing the load on the CPU to a minimum. The slave device is connected from the master device and another slave device is connected to the slave device, it can repeated to maximum 64 slave devices. The slave device has 3 types I/O mode, such as 16 bits input-only, 16 bits output-only, and 8bits input-output. The master device has 2 rings which can take 64 slaves each. Therefore, total I/O points covered by the master is 2048 points. The slave features 3 types of input/output function interchangeability by DIP switch settings. Library, application, and device driver software for the DIO system that have a secure and a convenient functionality are developed.

• Nuclear Engineering and Technology
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• v.42 no.2
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• pp.151-162
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• 2010

A severe accident training simulator that can simulate important severe accident phenomena and nuclear plant behaviors is developed. The simulator also provides several interactive control devices, which are helpful to assess results of a particular accident management behavior. A simple and direct dynamic linked library (DLL) data communication method is used for the development of the simulator. Using the DLL method, various control devices were implemented to provide an interactive control function during simulation. Finally, a training model is suggested for accident mitigation training and its performance is verified through application runs.

• Electronics and Telecommunications Trends
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• v.31 no.4
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• pp.65-76
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• 2016

특정 제조사의 단말 또는 운영체제에 의존성이 없는 플랫폼 독립적인 웹은 높은 이식성, 소프트웨어의 재활용, 개발 생산성, 풍부한 개발자 존재, 유지 보수 면에서 장점을 가지나, 화려한 UI/UX를 제공하는 네이티브 응용에 비해 낮은 성능으로 웹 기반의 응용 개발 및 보급이 크게 활성화되지 못했다. 한편 데스크톱은 물론 모바일 단말의 멀티코어 기반 Graphic Processing Unit(GPU), CPU 탑재 등 HW 고사양화와 웹 응용에서도 HW 가속 기능을 활용할 수 있는 표준 제공으로 성능 제약을 극복할 수 있게 되었다. 본고에서는 GPU 발전동향을 살펴보고, 고속 렌더링 및 병렬 연산처리를 요구하는 웹 응용이 GPU기반 HW 가속 기능을 활용할 수 있는 크로노스 그룹의 그래픽 가속(Web Graphics Library: WebGL) 및 컴퓨팅(Web Computing Language: WebCL) 지원 표준 규격을 정리한다. 또한, 최근 차세대 GPU Application Programming Interface(API)로 발표된 Vulkan에 대해 알아보고, 웹 고속화 기술에 적용 가능성에 대해 전망한다.

• International Journal of Internet, Broadcasting and Communication
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• v.5 no.2
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• pp.15-17
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• 2013

The web service companies develop the App support technique of the HTML5 base in the smart media system and smart TV competitively while the Web platform of the HTML5 base is legislated with the next generation national standard. It is essential to the web kernel, which is the common library of the operating system including the file, window, resource and network management is provided in order to support the various app developments of the HTML5 base effectually. Additionally, the web application program can support UI/UX function of the desktop user using the web browser and JavaScript drive and administration, window management function, and etc. is needed.

• Journal of the Korea Society of Computer and Information
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• v.21 no.4
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• pp.1-8
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• 2016

In small embedded systems including IoT devices, memory size is very small and it is important to reduce memory amount for execution of application programs. For multi-threaded applications, stack may consume a large amount of memory because each thread has its own stack of sufficiently large size for worst case. This paper presents an implementation of single stack multi-threading, called SSThread (Single Stack Thread), by sharing a stack for all threads to reduce stack memory size. By using SSThread, multi-threaded applications can be programmed based on normal C language environment and there is no requirement of transporting multi-threading operating systems. It consists of several library functions and various C macro definitions. Even though some functional restrictions in comparison to operating systems supporting complete multi-thread functionalities, it is very useful for small embedded systems with tiny memory size and it is simple to setup programming environment for multi-thread applications.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.443-444
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• 2008

A double-balanced frequency up-converter using the Gilbert cell structure has been designed with the TSMC $0.18\;{\mu}m$ CMOS library. The frequency up-converter consists of a Mixer core and IF / LO balun. Frequency Up-converter exhibits a 3.4 dB conversion gain with a - 7.6 dBm $P_{1dB}$ for IF power of -10 dBm and LO power of 0 dBm inputs. It also exhibits 92.2 % modulation depth as a ASK modulator.

• Journal of Institute of Control, Robotics and Systems
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• v.21 no.9
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• pp.827-835
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• 2015

In this paper, we present the implementation method of Dynamic Matrix Control(DMC) block for use with a Rapid Control Prototyping(RCP) system and consider the speed control of a DC motor using the developed DMC block. Firstly, we briefly introduce a lab-built RCP system. Secondly, we present a method for implementing a DMC block using C-language, which enables the DMC algorithm to be represented in a library block that can be used in a Simulink environment. Finally, we use the developed DMC block for the speed control of a DC motor, through which we show that the DMC-based control system can be easily implemented and applied to the real-time control of systems with relatively fast dynamics.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.144-147
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• 2000

Data security is an important issue in today's computer networks. In order to construct a safe infra in the open communication network, a cryptography is necessarily applied to several communication application fields like a high-speed networking system supporting real-time operation. A cryptography which has already realized by a software is designed by using a hardware to improve a throughput. In this paper, we design hardware architecture of IDEA by using a single iterative round method to improve a encryption throughput. In addition, we intend to develop a hardware design methodology that a specific cryptography operate with high-speed. The hardware model is described in VHDL and synthesized by the Samsung KG 80 Library in the Synopsys development software tool. With a system clock frequency 20MHz, this hardware permits a data conversion rate of more than 116 Mbit/s.

• Proceedings of the IEEK Conference
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• 2003.11a
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• pp.83-86
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• 2003

In this paper, we propose a new hardware architecture for integer transform, quantizer operation of a new video coding standard H.264/JVT. We describe the algorithm to derive hardware architecture emphasizing the importance of area for low cost and low power consumption. The proposed architecture has been verified by PCI-interfaced emulation board using APEX-II Altera FPGA and also by ASIC synthesis using Samsung 0.18 ${\mu}{\textrm}{m}$ CMOS cell library. The ASIC synthesis result shows that the proposed hardware can operate at 100 MHz, processing more than 1, 300 QCIF video frames per second. The hardware is going to be used as a core module when implementing a complete H.264 video encoder/decoder ASIC for real-time multimedia application.

• Journal of Plant Biotechnology
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• v.5 no.4
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• pp.197-200
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• 2003

Scalable Vector Graphics (SVG) has enabled a visually appealing, browser-based application for the display of Brassica sequences relative to Arabidopsis thaliana, and there are currently more than 70,000 B. napus Expressed Sequence Tags (ESTs) displayed. The client side of this browser is based on a Custom Graphical User Interface (CGUI) library which uses SVG, a new web graphics standard, to provide windowing functionality inside the web browser. This windowing functionality, combined with asynchronous data retrieval and client side rendering overcomes two of the key technology imposed drawbacks of current web based browsers: Fixed displays and frequent page reloads. The end result is an intuitive and enjoyable browsing experience. The browser is accessible online from the Brassica / Arabidopsis Genomics Initiative (http://brassica.agr.gc.ca). Inquiries about the browser should be directed to LewisCT@agr.gc.ca.