Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)
- 2000.11b
- /
- Pages.144-147
- /
- 2000
A VLSI Design of IDEA Cipher Algorithm Based On a Single Iterative Round Method
단일 라운드 프로세스 방식의 IDEA 암호 알고리즘의 하드웨어 설계
Abstract
Data security is an important issue in today's computer networks. In order to construct a safe infra in the open communication network, a cryptography is necessarily applied to several communication application fields like a high-speed networking system supporting real-time operation. A cryptography which has already realized by a software is designed by using a hardware to improve a throughput. In this paper, we design hardware architecture of IDEA by using a single iterative round method to improve a encryption throughput. In addition, we intend to develop a hardware design methodology that a specific cryptography operate with high-speed. The hardware model is described in VHDL and synthesized by the Samsung KG 80 Library in the Synopsys development software tool. With a system clock frequency 20MHz, this hardware permits a data conversion rate of more than 116 Mbit/s.
Keywords