• Journal of Satellite, Information and Communications
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• v.8 no.1
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• pp.54-60
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• 2013

The need for high performance of on-board computer (OBC) is essential due to the growing requirements and diversified missions, and so OBC has been developed on the basis of the standard design and reconfigurable modularization in order to improve the utilization of OBC for different missions. The processor in OBC of next generation satellite which is currently developed by KARI is adopted the LEON2-FT/AT697F processor based SPARC v8 as main processor and controls various devices such as SpaceWire, MIL-STD-1553B and CAN through PCI on the standardized communication chips. This paper presents the architecture and design of system software for LEON2-FT processor based on PCI, and development of PCI software component. Also it describes the porting of VxWorks 6.5 for LEON2-FT and the test under the simulation environment for LEON2-FT and PCI with communication chips.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.649-652
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• 2013

LEON3 is a 32-bit synthesisable processor based on the SPARC V8. It can be connected to AMBA 2.0 bus and has a 7-stage pipeline, IEEE-754 FPU and 256[KB] cache. It can be easily implemented using FPGA and used for a SoC design. DSU which comes with LEON3 can be used to control and monitor the operation of LEON3. And DSU makes it easy to set a debugging environment for the development of both hardware and software for an embedded systems based on LEON3. This paper presents the summary of the development of LEON3 monitoring software.

• Journal of Satellite, Information and Communications
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• v.9 no.4
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• pp.97-103
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• 2014

In order to verify normal operation of satellite OBC(On Board Computer), it is essential that processor monitoring and debugging. So we are using the GRMON of Aeroflex Gaisler. It provides a lot of features for debugging of LEON processor but we can't use that features on the NGSCB(Next Generation Spacecraft Computer Board) except a few things. So the cost-effectiveness is very low. And for hardware fault injection, we are using a method of modify satellite flight software, because we can't modify GRMON. This method can not guarantee normal operation of the satellite flight software. So in this paper we were developed the processor monitoring and fault injection tool for NGSCB.

• Journal of Institute of Control, Robotics and Systems
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• v.20 no.4
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• pp.474-479
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• 2014

LEON3 is a 32-bit synthesizable processor based on the SPARC V8. It can be connected to AMBA 2.0 bus and has a 7- stage pipeline, IEEE-754 FPU and 256[KB] cache. It can be easily implemented using FPGA and used for a SoC design. DSU which comes with LEON3 can be used to control and monitor the operation of LEON3. And DSU makes it easy to set a debugging environment for the development of both hardware and software for an embedded systems based on LEON3. This paper presents the summary of the debugging tool for LEON3 based embedded systems. The debugging tool can initialize the target hardware, find out how the target hardware is configured, load application code to a specified memory space and run that application code. To provide users a debugging environment, it can set breakpoints and control the operation of LEON3 correspondingly. And function call trace is one of key functions of the debugging tool.

• IEMEK Journal of Embedded Systems and Applications
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• v.14 no.1
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• pp.51-61
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• 2019

There are strict evaluation processes before using new processors to satellites. Engineers evaluate processors from various viewpoints including specification, development environment, and cost. From a viewpoint of computation power, manufacturers provide benchmark results with processors, and engineers decide which processors are adequate to their satellites by comparing the benchmark results with requirements of their satellites. However, the benchmark results depends on a test environment of manufacturers, and it is quite difficult to achieve similar performance in a target environment. Therefore, it is necessary to evaluate the processors in the target environment. This paper compares performance of a processor, AT697F/LEON2, in software testbed (STB) with three development boards of XC2V/LEON3, GR712RC/LEON3, and GR740/LEON4. Seven benchmark functions of Dhrystone, Stanford, Coremark, Whetstone, Flops, NBench, and MiBench are selected. Results are analyzed with hardware and software properties: hardware properties of core architecture, number of cores, cache, and memory; and software properties of build options and compilers. Based on the analysis, this paper describes a guideline for choosing processors for next generation satellites.

• Journal of Communications and Networks
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• v.4 no.3
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• pp.209-220
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• 2002

In this paper, we propose a hierarchical packet scheduling technique to closely approximate a hierarchical extension of the generalized processor sharing model, Hierarchical Generalized Processor Sharing (H-GPS). Our approach is to undertake the tasks of service guarantee and hierarchical link sharing in an independent manner so that each task best serves its own objective. The H-GPS model is decomposed into two separate service components: the guaranteed service component to consistently provide performance guarantees over the entire system, and the excess service component to fairly distribute spare bandwidth according to the hierarchical scheduling rule. For tight and harmonized integration of the two service components into a single packet scheduling algorithm, we introduce two novel concepts of distributed virtual time and service credit, and develop a packet version of H-GPS called Hierarchical Fair Queueing (HFQ). We demonstrate the layerindependent performance of the HFQ algorithm through simulation results.

• Journal of Satellite, Information and Communications
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• v.11 no.3
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• pp.65-71
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• 2016

Currently developing the OBC of the next-generation LEO satellite by Korea Aerospace Research Institute adopts the LEON2-FT/AT697F processor to achieve high performance. And various communication devices such as SpaceWire, MIL-STD-1553B, DMAUART and CAN Master are integrated to the separated standard communication FPGAs within the OBC, where they can be controlled by the processor and flight software (FSW) through PCI interface. The Actel 1553BRM IP core is used for the 1553B in the next-generation LEO OBC and the B1553BRM wrapper from Aeroflex Gaisler is used for connecting it to the AMBA bus in FPGA. This paper presents the design and development of PCI-based 1553B communication software, and describes the handling mechanism of 1553B operation in FSW task level. Also it shows the test results on real-hardware and simulator.

• KIISE Transactions on Computing Practices
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• v.20 no.9
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• pp.519-524
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• 2014

The operating systems in the system architecture, which is integrated several applications and modular electronic devices in the same computing device, demand partitioning technology for safety. Thus, operation system requires partition scheduler for partition scheduling. When we design partition scheduler in embedded system, which has small memory and low performance, such as space system, we must consider not only performance but also memory. In this paper, we introduces a linux-based memory efficient partition scheduler using partition bitmap. This partition scheduler demands small memory space and produce low partition switching overhead. The prototype was executed on a LEON4 processor, which is the Next Generation Multicore Processor (NGMP) in the space sector. In evaluation, this prototype shows accuracy, additional memory space and low partition switching overhead.

• IEMEK Journal of Embedded Systems and Applications
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• v.15 no.4
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• pp.177-187
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• 2020

Virtualization with hypervisors is one of emerging topics in multicore processors for space. Hypervisors are software layers to make several independent virtualized environments on one processor. Since all hardware resources are virtualized and distributed only by hypervisors, overall performance of processors can be improved by fully utilizing the resources. However at the same time, there are overheads for virtualizing and distributing hardware resources. Satellites are one of hard real time systems, and performance degradation with overheads should be analyzed thoroughly. Previous research on the overheads focused on single core systems. Even the overheads were analyzed in multicore systems, SMP environment was not fully included. This paper builds SMP environment with XtratuM, one of hypervisors for space missions, and analyzes performance degradation with overheads. Two boards of GR712RC with 2 LEON3FT CPUs and GR740 with 4 LEON4 CPUs are used in experiments. On each board, SMP benchmark functions are executed on SMP environment with XtratuM and on that without XtratuM respectively. Results are analyzed to find timing characteristics including overheads. Finally, applicability of the XtratuM to flight software in SMP is also reviewed.

• Journal of Satellite, Information and Communications
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• v.12 no.3
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• pp.108-113
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• 2017

The OBCP called 'operator on board' is that of a procedure to be executed on-board, which can be easily be loaded, executed, and also replaced, without modifying the remainder of the FSW. The use of OBCP enhances the on-board autonomy capabilities and increases the robustness to ground stations outages. The OBCP engine which is the core module of OBCP component in the FSW interprets and executes of the procedures based on script language written using a high-level language, possibly compiled, and it is relying on a virtual machine of the OBCP engine. FSW team in KARI has studied OBCP since 2010 as FSW team's internal projects, and made some OBCP engines such as Java KVM, RTCS/C and KKOMA on ERC32 processor target only for study. Recently we have been studying ESA's OBCP standard and implementing Lua and MicroPython on LEON2-FT/AT697F processor target as the OBCP engine. This paper presents the design and implementation of Lua for the OBCP engine on AT697F processor with VxWorks RTOS, and describes the evaluation result and performance of the OBCP engine.