• 제목/요약/키워드: Leakage current density

검색결과 482건 처리시간 0.021초

박막트랜지스터 게이트 절연막 응용을 위한 불화막 특성연구 (The Study of Fluoride Film Properties for Thin Film Transistor Gate Insulator Application)

  • 김도영;최석원;안병재;이준신
    • 대한전기학회논문지:전기물성ㆍ응용부문C
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    • 제48권12호
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    • pp.755-760
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    • 1999
  • Various fluoride films were investigated for a gate insulator of thin film transistor application. Conventional oxide containing materials like $SiO_2\;Ta_2O_5\; and \; Al_2O_3$ exhibited high interface states which lead to an increased threshold voltage and poor stability of TFT. In this paper, we investigated gate insulators using a binary matrix system of fluoride such as $CaF_2,\; SrF_2\; MgF_2,\; and\; BaF_2$. These materials exhibited an improvement in lattice mismatch, interface state and electrical stability. MIM and MIS devices were employed for an electrical characterization and structural property examination. Among the various fluoride materials, $CaF_2$ film showed an excellent lattice mismatch of 5%, breakdown electric field higher than 1.2MV/cm and leakage current density of $10^{-7}A/cm^2$. MIS diode having $Ca_2$ film as an insulation layer exhibited the interface states as low as $1.58\times10^{11}cm^{-2}eV^{-1}$. This paper probes a possibility of new gate insulator materials for TFT applications.

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ONO 버퍼층을 이용한 Metal/Ferroelectrics/Insulator/Semiconductor 구조의 제작 및 특성 (Fabrication and Properties of Metal/Ferroelectrics/Insulator/Semiconductor Structures with ONO buffer layer)

  • 이남열;윤성민;유인규;류상욱;조성목;신웅철;최규정;유병곤;구진근
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2002년도 하계학술대회 논문집
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    • pp.305-309
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    • 2002
  • We have successfully fabricated a Metal-Ferroelectric-Insulator-Semiconductor (MFIS) structure using Bi$\sub$4-x/La$\sub$x/Ti$_3$O$\sub$12/ (BLT) ferroelectric thin film and SiO$_2$/Nitride/SiO$_2$ (ONO) stacked buffer layers for single transistor type ferroelectric nonvolatile memory applications. BLT films were deposited on 15 nm-thick ONO buffer layer by sol-gel spin-coating. The dielectric constant and the leakage current density of prepared ONO film were measured to be 5.6 and 1.0 x 10$\^$-8/ A/$\textrm{cm}^2$ at 2MV/cm, respectively, It was interesting to note that the crystallographic orientations of BLT thin films were strongly effected by pre-bake temperatures. X-ray diffraction patterns showed that (117) crystallites were mainly detected in the BLT film if pre-baked below 400$^{\circ}C$. Whereas, for the films pre-baked above 500$^{\circ}C$, the crystallites with preferred c-axis orientation were mainly detected. From the C-V measurement of the MFIS capacitor with c-axis oriented BLT films, the memory window of 0.6 V was obtained at a voltage sweep of ${\pm}$8 V, which evidently reflects the ferroelectric memory effect of a BLT/ONO/Si structure.

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(Pr, Co, Cr, La)-doped ZnO 바리스터의 전기적 특성에 미치는 소결온도효과 (Effects Sintering Temperature on Electrical Properties of (Pr, Co, Cr, La)-doped ZnO Varistors)

  • 남춘우
    • 한국전기전자재료학회논문지
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    • 제19권12호
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    • pp.1085-1091
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    • 2006
  • The microstructure, electrical properties, and its stability of (Pr, Co, Cr, La)-doped ZnO varistors were investigated at different sintering temperatures in the range of $1230{\sim}1300^{\circ}C$. As the sintering temperature increased, the sintered density increased from 5.50 to $5.77g/cm^3$, the varistor voltage decreased from 777.9 to 108.0 V/mm, the nonlinear coefficient decreased from 77.0 to 7.1, and the leakage current increased from $0.4{\mu}A\;to\;50.6{\mu}A$. On the other hand, the donor concentration increased from $0.90{\times}10^{18}\;to\;2.59{\times}10^{18}/cm^3$ and the barrier height decreased from 1.89 to 0.69 eV with increasing temperature. The stability of nonlinear electrical properties was obtained from sintering temperature of $1260^{\circ}C$. The varistors sintered at $1260^{\circ}C$ marked the high electrical stability, with $%{\Delta}V_{1mA}=+1.9%,\;%{\Delta}a=10.6%,\;and\;%{\Delta}I_L=+20%$ for DC accelerated aging stress state of $0.95V_{1mA}/150^{\circ}C/24h$.

6H-SiC 위에 형성한 에피택시 AIN 박막 구조에 대한 전기적 특성의 평가온도 의존성 (Temperature Dependence on Electrical Characterization of Epitaxially Grown AIN film on 6H-SiC Structures)

  • 김용성;김광호
    • 한국전기전자재료학회논문지
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    • 제19권1호
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    • pp.18-22
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    • 2006
  • Epitaxial aluminum nitride films on 6H-SiC (0001) were fabricated using reactive RF magnetron sputtering and post-deposition rapid thermal annealing. The electrical properties of AIN films depending on film thickness and measurement temperature have been observed. Full width at half maximum of AIN (0002) was $0.1204^{\circ}$ (about 430 arcsec) X-ray rocking curve results. The equivalent oxide thickness (EOT) of AIN film was estimated as about 10 nm and the leakage current density was within the order of $10^{-8} 4/cm^2$. The dielectric constant of AIN film estimated from the accumulation region of C-V curve measured at $300^{\circ}C$ was 8.3. The dynamic dielectric constant was obtained as 5.1 from J vs. 1/T plots at the temperature ranging from R.T. to $300^{\circ}C$ From above, estimation temperature dependance of the electrical properties of Al/AIN/SiC MIS devices was affirmed and useful data compilation for the reliabilities of SiC MIS is expected.

플래시 및 바이트 소거형 EEPROM을 위한 고집적 저전압 Scaled SONOS 비휘발성 기억소자 (High Density and Low Voltage Programmable Scaled SONOS Nonvolatile Memory for the Byte and Flash-Erased Type EEPROMs)

  • 김병철;서광열
    • 한국전기전자재료학회논문지
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    • 제15권10호
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    • pp.831-837
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    • 2002
  • Scaled SONOS transistors have been fabricated by 0.35$\mu\textrm{m}$ CMOS standard logic process. The thickness of stacked ONO(blocking oxide, memory nitride, tunnel oxide) gate insulators measured by TEM are 2.5 nm, 4.0 nm and 2.4 nm, respectively. The SONOS memories have shown low programming voltages of ${\pm}$8.5 V and long-term retention of 10-year Even after 2 ${\times}$ 10$\^$5/ program/erase cycles, the leakage current of unselected transistor in the erased state was low enough that there was no error in read operation and we could distinguish the programmed state from the erased states precisely The tight distribution of the threshold voltages in the programmed and the erased states could remove complex verifying process caused by over-erase in floating gate flash memory, which is one of the main advantages of the charge-trap type devices. A single power supply operation of 3 V and a high endurance of 1${\times}$10$\^$6/ cycles can be realized by the programming method for a flash-erased type EEPROM.

Sol-gel 법으로 제작된 BST 박막의 Bi 첨가에 따른 구조적, 유전적 특성 (Fabrication of BST Thin films with Bi Addition by Sol-gel Method and their Structural and Dielectric Properties)

  • 김경태;김창일
    • 한국전기전자재료학회논문지
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    • 제17권8호
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    • pp.852-858
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    • 2004
  • An alkoxide-based sol-gel method was used to fabricate $Ba_{0.6}Sr_{0.4}TiO_{3}$thin films doped by Bi from 5 to 20 mol% on a Pt/Ti/$SiO_2$/Sisubstrate. The structural and dielectric properties of BST thin films were investigated as a function of Bi dopant concentration. The dielectric properties of the Bi doped BST films were strongly dependent on the Bi contents. The dielectric constant and dielectric loss of the films decreased with increasing Bi content. However, the leakage current density of the 10 mol% Bi doped $Ba_{0.6}Sr_{0.4}TiO_{3}$ thin film showed the lowest value of 5.13$\times 10^{-7} A/{cm}^2$ at 5 V. The figure of merit (FOM) reached a maximum value of 32.42 at a 10 mol% Bi doped $Ba_{0.6}Sr_{0.4}TiO_{3}$thin films. The dielectric constant, loss factor, and tunability of the 10 mol% Bi doped $Ba_{0.6}Sr_{0.4}Tio_{3}$ thin films were 333, 0.0095, and 31.1%, respectively.

기판에 따른 BST 박막의 RF Power 의존성 (Study on RF power dependence of BST thin film by the different substrates)

  • 최명률;이태일;박인철;김홍배
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2002년도 하계학술대회 논문집
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    • pp.22-25
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    • 2002
  • In this paper, we deposited MgO buffer layer on p-type (100)Si substrate in the condition of substrate temperature 400$^{\circ}C$, working gas ratio Ar:O$_2$=80:20, RF Power 50W, working pressure 10mtorr, and the thickness of the film was about 300${\AA}$. Then we deposited Ba$\sub$0.5/Sr$\sub$0.5/TiO$_3$ thin film using RF Magnetron sputtering method on the MgO/Si substrate in various RF power of 25W, 50W, 75W. The film deposited in 50W showed the best crystalline from the XRD measurement. To know the electrical properties of the film, we manufactured Al/BSTMgO(300${\AA}$)/Si/Al structure capacitor. In the result of I-V measurement, The leakage current density of the capacitor was lower than 10$\^$-7/A/$\textrm{cm}^2$ at the range of ${\pm}$150kV/cm. From C-V characteristics of the capacitor, can calculate the dielectric constant and it was 305. Finally we deposited BST thin film on bare Si substrate and (100)MgO substrate in the same deposition condition. From the comparate of the properties of these samples, we found the properties of BST thin film which deposited on MgO/Si substrate were better than on bare Si substrate and similar to on MgO substrate.

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열처리 온도에 따른 Pt/SBT/Pt 캐패시터의 유전특성 (Dielectric Properties of SBT capacitor with annealing temperatures)

  • 조춘남;오용철;정일형;김진사;신철기;최운식;김충혁;이준웅
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2001년도 하계학술대회 논문집 C
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    • pp.1546-1548
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    • 2001
  • The $Sr_{0.8}Bi_{2.4}Ta_2O_9$(SBT) thin films are deposited on Pt-coated electrode(Pt/$TiO_2$/ $SiO_2$/Si) using RF magnetron sputtering method. With increasing annealing temperature from 600[$^{\circ}C$] to 850[$^{\circ}C$], Bi-layered perovskite phase was crystallized above 650[$^{\circ}C$]. The dielectric constant is 213 at annealing temperature of 750[$^{\circ}C$] and dielectric loss have a stable value within 0.1. Leakage current density is $1.01{\times}10^{-8}A/cm^2$ at annealing temperature of 750[$^{\circ}C$].

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Pt/LiNbO3/AlN/Si(100) 구조를 이용한 MFIS 커패시터의 전기적 특성 (Electric Properties of MFIS Capacitors using Pt/LiNbO3/AlN/Si(100) Structure)

  • 정순원;김광호
    • 한국전기전자재료학회논문지
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    • 제17권12호
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    • pp.1283-1288
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    • 2004
  • Metal-ferroelectric-insulator-semiconductor(WFIS) capacitors using rapid thermal annealed LiNbO$_3$/AlN/Si(100) structure were fabricated and demonstrated nonvolatile memory operations. The capacitors on highly doped Si wafer showed hysteresis behavior like a butterfly shape due to the ferroelectric nature of the LiNbO$_3$ films. The typical dielectric constant value of LiNbO$_3$ film in the MFIS device was about 27, The gate leakage current density of the MFIS capacitor was 10$^{-9}$ A/cm$^2$ order at the electric field of 500 kV/cm. The typical measured remnant polarization(2P$_{r}$) and coercive filed(Ec) values were about 1.2 $\mu$C/cm$^2$ and 120 kV/cm, respectively The ferroelectric capacitors showed no polarization degradation up to 10$^{11}$ switching cycles when subjected to symmetric bipolar voltage pulses of 1 MHz. The switching charges degraded only by 10 % of their initial values after 4 days at room temperature.e.

LDD 공정 조건에 따른 편치쓰루 및 핫 캐리어 효과에 관한 연구 (A Study on Punchthrough and Hot-carrier Effects as LDD Process Parameters)

  • 안태현;김남훈;김창일;서용진;장의구
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1998년도 하계학술대회 논문집 D
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    • pp.1367-1369
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    • 1998
  • To achieve the ULSI goals of higher density, greater performance and operation speed have been scaled down. However, the reduction of channel length cause undesirable problems such as drop of punchthrough voltage, hot-carrier degradation and high leakage current, etc.. It is shown that the device characteristics depend on process parameters. In this Paper, we catched hold of trends of hot-carrier effects and punchthrough voltages due to variation of some process parameters such as LDD doses(P), spacer lengths, channel doses($BF_2$) and $V_T$ adjusting channel implantation energies using design trend curve (DTC). As the LDD and channel doses increased, hot-carrier phenomena became more severe, and punchthrough voltage was decreased. It were represented that punchthrough and hot carrier effects were critically depend on LDD and channel doses.

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