• Journal of IKEEE
• /
• v.12 no.4
• /
• pp.211-216
• /
• 2008

This paper proposes an 8${\times}$8 bit parallel multiplier using MOS current-mode logic (MCML) circuit for low power consumption. The proposed circuit has a structure of low-power MOS current-mode logic circuit with sleep-transistor to reduce the leakage current. The sleep-transistor is used to PMOS transistor to minimize the leakage current. Comparing with the conventional MOS current-model logic circuit, the circuit achieves the reduction of the power consumption in sleep mode by 1/50. The designed multiplier is achieved to reduce the power consumption by 10.5% and the power-delay-product by 11.6% compared with the conventional MOS current-model logic circuit. This circuit is designed with Samsung 0.35 ${\mu}m$ standard CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

• Journal of Communications and Networks
• /
• v.12 no.2
• /
• pp.158-167
• /
• 2010

The energy efficiency of wireless infrastructure and terminals has been drawing renewed attention of late, due to their significant environmental cost. Emerging green communication paradigms such as cognitive radios, are also imposing the additional requirement of flexibility. This dual requirement of energy efficiency and flexibility poses new design challenges for implementing radio functional blocks. This paper focuses on the area vs. power trade-offs for the type of channel filters that are required in the digital frontend of a flexible, energy-efficient radio. In traditional CMOS circuits, increased area was traded for reduced dynamic power consumption. With leakage power emerging as the dominant mode of power consumption in nanoscale CMOS, these trade-offs must be revisited due to the strong correlation between area and leakage power. The current work discusses how the increased timing slacks obtained by increasing the parallelism can be exploited for overall power reduction even in nanoscale circuits. In this context the paper introduces the notion of 'area efficiency' and a metric for evaluating it. The proposed metric has also been used to compare the area efficiencies of different classes of time-shared filters.

• Journal of the Korean Society for Railway
• /
• v.13 no.5
• /
• pp.516-520
• /
• 2010

Parametric study has been conducted to calculate the capacity of vacuum pump system that will be used to maintain the pressure of the tube structure under atmosphere level. Recently many railroad researchers pay attention to the tube train system as one of the super high speed transportation system. To achieve the super high speed, the inside of tube system should be maintained at low pressure level. In the low pressure environment, it is well known that air resistance of train is drastically decreased. Vacuum pump system will be used to make low pressure state for tube structure, exhaust the leakage air and supplement additional vacuum pumping. As results of these studies, we get the lump capacity of vacuum pump for various parameters. These results can be applied to analyze the effects of the reduction of air resistance.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2014.02a
• /
• pp.182-182
• /
• 2014

Multiferroic materials have attracted much attention due to their own fascinating fundamental physical properties and potential technological applications to magnetic/ferroelectric data storage systems, quantum electromagnets, spintronics, and sensor devices. Among single-phase multiferroic materials, $BiFeO_3$, in particular, has received considerable attention because the enhanced ferromagnetism was found by the Fe-site ion substitution with magnetic ions. The structural, the magnetic and the ferroelectric properties of polycrystalline $BiFe_{1-x}Ni_xO_3$ (x=0, 0.01, 0.02, 0.03 and 0.05), which were prepared by the solid-state reaction and the rapid-sintering method, have been investigated. The x-ray diffraction patterns reveal that all the samples are in single phase and show rhombohedral structure with R3c space group. The magnetic properties are enhanced according to the doping content. The Ni-doped $BiFeO_3$ samples exhibit lossy P-E loop due to the oxygen vacancy. The leakage current density of Ni-doped samples (x=0.01 and 0.02) is increased by four orders of magnitude. On the other hand, the x=0.03 and 0.05 samples show the relative reduction of the leakage current.

• Proceedings of the Korean Institute of Building Construction Conference
• /
• 2017.05a
• /
• pp.127-128
• /
• 2017

Tests are conducted according to the ISO TS 16774, Part 3 standard for quality management of leakage repair materials used in cracks in underground concrete structures. These test methods are performed indirectly using a nonwoven fabric on a chalet containing leak repair materials. However, it is considered that it is appropriate to verify the resistance of the repair material, which is required to be applied directly to the cracks in the actual field and to exhibit the resistance of the flow velocity. In this study, mass change was measured by using nonwoven fabric and nonwoven fabric. As a result, both methods showed an increase in mass, which indicated that the maintenance material itself contained a large amount of water, and that the mass change occurred depending on the drying state. Also, depending on the use of nonwoven fabric, the error due to the indirect test could not be ruled out. Therefore, further verification is needed, and it is considered that the test for change of mass reduction measurement is necessary according to the drying time of other types of the same series.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2012.02a
• /
• pp.388-388
• /
• 2012

In this letter, We have investigated cell characteristics of the alloy FePt-NDs charge trapping memory capacitors with high-k $Al_2O_3$ dielectrics as a blocking oxide. The capacitance versus voltage (C-V) curves obtained from a representative MOS capacitor embedded with FePt-NDs synthesized by the post deposition annealing (PDA) treatment process exhibit the window of flat-band voltage shift, which indicates the presence of charge storages in the FePt-NDs. It is shown that NDs memory with high-k $Al_2O_3$ as a blocking oxide has performance in large memory window and low leakage current when the diameter of ND is below 2 nm. Moreover, high-k $Al_2O_3$ as a blocking oxide increases the electric field across the tunnel oxide, while reducing the electric field across the blocking layer. From this result, this device can achieve lower P/E voltage and lower leakage current. As a result, a FePt-NDs device with high-k $Al_2O_3$ as a blocking oxide obtained a~7V reduction in the programming voltages with 7.8 V memory.

• Proceedings of the Korean Institute of Building Construction Conference
• /
• 2006.05a
• /
• pp.1-4
• /
• 2006

A down construction method is frequently used in these days to reduce popular discontent and to assure sufficient working space at early stage in downtown area. There are two main problems in the existing down construction method. One is a confliction between frame works and excavation works, and the other is a cold joint in retaining wall which is unavoidable due to a sequence of concrete placement and induces a water leakage. Therefore, a new method is needed to overcome these problems. The CWS (buried wale Continuous Wall System) method was developed by authors. By replacing RC perimeter beam with embedded steel wale, the steel frame works of substructure can be simplified and the water leakage can be prevented using continuous retaining wall. Consequently, the improved duality and reduction of construction period can be obtained from CWS method.

• The KIPS Transactions:PartA
• /
• v.15A no.2
• /
• pp.69-74
• /
• 2008

This paper proposes a structure of low-power MOS current-mode logic circuit with sleep-transistor to reduce the leakage current. The sleep-transistor is used to high-threshold voltage transistor to minimize the leakage current. The $16\;{\times}\;16$ bit parallel multiplier is designed by the proposed circuit structure. Comparing with the conventional MOS current-model logic circuit, the circuit achieves the reduction of the power consumption in sleep mode by 1/50. This circuit is designed with Samsung $0.35\;{\mu}m$ CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.21 no.2
• /
• pp.104-110
• /
• 2008

In this paper we proposed a new source-drain structure for N-type MOSFET which can suppress the output resistance reduction of a device in saturation region due to soft break down leakage at high drain voltage when the gate is biased around relatively low voltage. When a device is generally used as a switch at high gate bias the current level is very important for the operation. but in electronic circuit like an amplifier we should mainly consider the output resistance for the stable voltage gain and the operation at low gate bias. Hence with T-SUPREM simulator we designed devices that operate at low gate bias and high gate bias respectively without a extra photo mask layer and ion-implantation steps. As a result the soft break down leakage due to impact ionization is reduced remarkably and the output resistance increases about 3 times in the device that operates at the low gate bias. Also it is expected that electronic circuit designers can easily design a circuit using the offered N-type MOSFET device with the better output resistance.

• Journal of the Korea Institute of Building Construction
• /
• v.6 no.2 s.20
• /
• pp.81-89
• /
• 2006

A down construction method is frequently used in these days to reduce popular discontent and to assure sufficient working space at early stage in downtown area. There are two main problems in the existing down construction method. One is a confliction between frame works and excavation works, and the other is a cold joint in retaining wall which is unavoidable due to a sequence of concrete placement and induces a water leakage. Therefore, a new method is needed to overcome these problems. The CWS (buried wale Continuous Wall System) method was developed by authors. By replacing RC perimeter beam with embedded steel wale, the steel frame works of substructure can be simplified and the water leakage can be prevented using continuous retaining wall. Consequently, the improved qualify and reduction of construction period can be obtained from CWS method.