• Proceedings of the Korea Committee for Ocean Resources and Engineering Conference
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• 2002.05a
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• pp.86-91
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• 2002

The production part requiring multiple processes such as piecing, blanking and notching, are performed with a high production rates in progressive die. In order to prevent the dejects of process result, the optimum of strip process layout design, die design, die making, and tryout with inspection etc. are needed. According to these factors of die development process, they required theory and practice of metal working process and its phenomena, die structure, machining conditions for die making, die materials, heat treatment of die camponents, know-how and so on. In this study, we designed and analyzed die camponents also simulated the strip process layout of multiple stage drawing by DEFORM. Especially the result of tryout and its analysis become to the feature of this study.

• Journal of the Korean housing association
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• v.13 no.6
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• pp.21-29
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• 2002

The purpose of this study is to investigate the changes of architectural characteristics of the rural houses in Jeju area for the last half a century. 72 houses in eight villages, which have been spontaneously renovated or added, were chosen as the rersearch samples. The subjects were classified into three groups-traditional, modernized, and contemporary houses-mainly by their construction years. Based upon these classification, the factors of change and continuation in building layout and spatial composition of dwellings have been investigated. As the results, Jeju rural houses show the tendency of the various and rapid changes in overall shape and spatial composition, but the traditional concepts of composition in plan has been maintained. Especially, the open structure of three-folded houses and the utilization of traditional floor system have been maintained as major design concepts to compose a house.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2007.05a
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• pp.1023-1026
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• 2007

Optimal damping layout of the constrained viscoelastic damping layer on beam is identified with temperatures by using a gradient-based numerical search algorithm. An optimal design problem is defined in order to determine the constrained damping layer configuration. A finite element formulation is introduced to model the constrained damping layer beam. The four-parameter fractional derivative model and the Arrhenius shift factor are used to describe dynamic characteristics of viscoelastic material with respect to frequency and temperature. Frequency-dependent complex-valued eigenvalue problems are solved by using a simple resubstitution algorithm in order to obtain the loss factor of each mode and responses of the structure. The results of the numerical example show that the proposed method can reduce frequency responses of beam at peaks only by reconfiguring the layout of constrained damping layer within a limited weight constraint.

• Proceedings of the Korea Committee for Ocean Resources and Engineering Conference
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• 2000.04a
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• pp.35-39
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• 2000

The piercing and blanking of thin sheet metal working is specified division in press die design and making. In order to prevent the detects, the optimum design of the production part, strip process layout, die design, die making and try out etc. are necessary the analysis of effective factors. For example, theory and practice of metal shearing process and its phenomena, die structure, machine tool working for die making, die materials and its heat treatment, metal working in industrial and its know how etc. In this study, we analyzed whole of data base, theoretical back ground of metal working process, and then performed the progressive die tryout with the screw press. This study regards to the aim of small quantity of production parts press working. Part 1 of this study reveals with production part and strip process layout design.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.914-917
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• 1999

The paper describes a 17 $\times$ 17-b multiplier using the Radix-4 Booth’s algorithm. which is suitable for 32-bit RISC/DSP microprocessors. To minimize design area and achieve improved speed, a 2-stage pipeline structure is adopted to achieve high clock frequency. Each part of circuit is modeled and optimized at the transistor level, verification of functionality and timing is performed using HSPICE simulations. After modeling and validating the circuit at transistor level, we lay it out in a 0.35 ${\mu}{\textrm}{m}$ 1-poly 4-metal CMOS technology and perform LVS test to compare the layout with the schematic. The simulation results show that maximum frequency is 330MHz under worst operating conditions at 55$^{\circ}C$ , 3V, The post simulation after layout results shows 187MHz under worst case conditions. It contains 9, 115 transistors and the area of layout is 0.72mm by 0.97mm.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.3 no.4
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• pp.43-49
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• 2004

The production parts have required multiple processes such as drawing, piercing, blanking and notching etc. are performed with a high production rates in progressive die. In order to prevent the defects of process result, the optimization of strip process layout design, die design, die making, and tryout etc. are needed. According to these factors of die development process, it has been required that the theory and practice of metal working process and its phenomena, die structure, machining conditions for die making, die materials, heat treatment of die components, processing know-how and so on. In this study, we designed and analyzed die components through the carrying out of upper relevant matters also simulated the strip process layout of multiple stage drawing by DEFORM. Especially the result of tryout and its analysis became to the feature of this study with a system of PDDC(Progressive Die design by computer).

• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 2002.10a
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• pp.341-346
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• 2002

The production part requiring multiple processes such as piecing, blanking and notching are performed with a high production rates in progressive die. In order to prevent the defects of process result, the optimum of strip process layout design, die design, die making, and tryout with inspection etc. are needed. According to these factors of die development process, they required theory and practice of metal working process and its background, die structure, machining conditions for die making, die materials, heat treatment of die components, know-how and so on. In this study, we designed and analyzed die components also simulated the strip process layout of multiple stage drawing by DEFORM. Especially the result of tryout and its analysis become to the feature of this study.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.9
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• pp.65-75
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• 1992

In this paper, we introduce an integrated layout design system, SOLGER. Our system incorporates useful design tools : a powerful layout editor, a coherent access mechanism for large volumes of design data, an incremental design rule checker for hierarchical design environment, node extractor and electrical rule checker, a technology capture which is used for defining technology-specific information, and a procedural design environment for user customization. Also, we present a modified corner-stitching data structure which allows 45$^{\circ}$-angled bilateral edges. Users are provided with a multi-window design environment and a menu-driven interface. SOLGER is being used for VLSI designs practically.

• Proceedings of the Korean Institute of Building Construction Conference
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• 2019.11a
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• pp.14-15
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• 2019

In this paper, it was tried to prove the possibility and effect of coordinate measurement by using MEP layout equipment at the construction stage, and to propose a method to improve measurement accuracy during construction. For this study, the passenger terminal site, which is a long span structure, was selected and compared with three dimensional CAD drawings and construction measurement results using MEP layout equipment for the precise construction of long-span irregular curved roof layers. As a result, it was found that it is possible to construct three-dimensional curved roof layers using MEP layout equipment through measurement and analysis.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.4
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• pp.35-42
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• 2013

In this paper, the analog performance of FinFET structure was estimated by extracting the DC/AC characteristics of the 22 nm process FinFET structures with different layout considering spacer and SEG using 3D device simulator, Sentaurus. Based on the analysis results, layout methods to enhance the analog performance of multi-fin FinFET structures are proposed. By adding the spacer and SEG structures, the drive current of 1-fin FinFET increases. However, the unity gain frequency, $f_T$, reduces by 19.4 % due to the increase in the total capacitance caused by the added spacer. If the process element is not included in multi-fin FinFET, replacing 1-finger with 2-finger structure brings approximately 10 % of analog performance improvement. Considering the process factors, we propose methods to maximize the analog performance by optimizing the interconnect and gate structures.