• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.8
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• pp.799-805
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• 2004

Two dimensional MEDICI simulator is used to study the characteristics of latch-up current of Dual Gate Emitter Switched Thyristor. The simulation is done in terms of the current-voltage characteristics, latch-up current density, ON-voltage drop and electrical property with the variations of p-base impurity concentrations. Compared with the other power devices such as MOS Controlled Cascade Thyristor(MCCT), Conventional Emitter Switched Thyristor(C-EST) and Dual Channel Emitter Switched Thyristor(DC-EST), Dual Gate Emitter Switched Thyristor(DG-EST) shows to have the better electrical characteristics, which is the high latch-up current density and low forward voltage-drop. The proposed DG-EST which has a non-planer p-base structure under the floating $N^+$ emitter indicates to have the better characteristics of latch-up current and breakover voltage.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.44 no.2
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• pp.222-227
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• 1995

A new IGBT structure, which may suppress latch-up phenomena considerably, is proposed and verified by MEDICI simulation. The proposed structure employing the segmented $n^{+}$ buffer layer increases latch-up current capability due to suppression of the current flowing through the resistance of $p^{-}$ well, $R_{p}$, which is the main cause of latch-up phenomena without degradation of forward characteristics. The length of the $n^{+}$ buffer layer is investigated by considering the trade-off between the latch-up current capability and the forward voltage drop. The segmented $N^{+}$ buffer layer results in better latch-up immunity in comparison with the uniform buffer layer.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.283-285
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• 2001

In this paper, a new lateral insulated gate bipolar transistor (LIGBT) is proposed to improve the latch-up performance without current path underneath the n+ cathode region. The improvement of latch-up performance is verified using the two-dimensional simulator MEDICI and the simulation results on the latch-up current density are 3.12${\times}$10$\^$-4/ A/$\mu\textrm{m}$ for the proposed LIGBT and 0.94${\times}$10$\^$-4/ A/$\mu\textrm{m}$ for the conventional LIGBT. The proposed SOI LIGBT exhibits 3 times larger latch-up capability than the conventional SOI LIGBT.

• Transactions on Electrical and Electronic Materials
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• v.2 no.4
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• pp.30-32
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• 2001

In this paper, a new silicon-on-insulator (SOI) lateral insulated gate bipolar transistor (LIGBT) is proposed to improve the latch-up performance without current path underneath the n$^{+}$ cathode region. The improvement of latch-up performance is verified using the two- dimensional simulator MEDICI and the simulation results on the latch-up current density are 4468 A/cm2 for the proposed LIGBT and 1343 A/$\textrm{cm}^2$ for the conventional LIGBT. The proposed SOI LIGBT exhibits 3 times larger latch-up capability than the conventional SOI LIGBT.T.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.8
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• pp.898-907
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• 1992

This paper deals with a detailed analysis of CMOS latch up dependancies on the layout and geo-metrical demensions on the mask using same materials and same processes. For this purpose, six different layout models depending upon the N+ / P+ spacing and three different guard ring models have been gesigned, fabricated, and tested. As a result, common emitter current gain, shunt resistance, and holeing current versus N+/P+ spacing have been measured and analyzed experimentally. Also the fact that guard ring is sffective in reducing the latchup possibility has been verified through this study.

• Proceedings of the KIEE Conference
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• 1993.11a
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• pp.240-242
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• 1993

A novel structure, which can suppress latch-up phenomena, is proposed and verified by the PISCESIIB simulation. It is shown that this structure employing the selective N+ buffer layer increases latch-up current density due to suppression of the current flowing through the p-body. The width of the N+ buffer layer is optimized considering the trade-off between the latch-up current density and the forward voltage drop. The selective buffer layer results in an improved trade-off relationship compared with the uniform buffer layer.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.10
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• pp.1034-1040
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• 2004

The latch-up current and switching characteristics of MOS-Controlled Thyristor(MCT) are studied with variation of the channel length and impurity concentration. The proposed MCT power device has the lateral structure and P-epitaxial layer in substrate. Two dimensional MEDICI simulator is used to study the latch-up current and forward voltage-drop from the characteristics of I-V and the switching characteristics with variation of impurity concentration. The channel length and impurity concentration of the proposed MCT power device show the strong affect on the anode current and turn-off time. The increase of impurity concentration in P and N channels is found to give the increase of latch-up current and forward voltage-drop.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.441-444
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• 1998

This paper is concerned with researching latch-up immune CMOS structure was performed. By the simulation results, the connecting layer had more effect than the buried layer to latch-up immune. When the connecting layer was the dose 1*10$^{14}$ /cm$^{2}$ and the energy 500KeV, the trigger current was more 0.6mA/.mu.m and the trigger voltage was 6V. The more the connecting layer dose was lower, the more the latch-up immune characteristics was butter.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.9
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• pp.54-61
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• 1998

A new Triple well structure is proposed for improved latch-up immunity at deep submicron CMOS device. Optimum latch-up immunity process condition is established and analyzed with varying ion implantation energy and amount of dose and also compared conventional twin well structure. Doping profile and structure are investigated using ATHENA which is process simulator, and then latch-up current is calculated using ATLAS which is device simulator. Two types of different process are affected by latch-up characteristics and shape of doping profiles. Finally, we obtained the best latch-up immunity with 2.5[mA/${\mu}{m}$] trigger current using 2.5 MeV implantation energy and 1$\times$10$^{14}$ [cm$^{-2}$ ] dose at p-well

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.111-118
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• 2008

In this paper, novel latch-up prevention method that employs power-up sequential switches has been proposed to relieve latch-up problem in liquid crystal display (LCD) driver ICs. These sequential switches are inserted in the 2'nd and 3'rd boosting stages, and are used to short the emitter-base terminals of parasitic p-n-p-n circuit before relevant boosting stages are activated during power-up sequence. To verily the performance of the proposed method, test chips were designed and fabricated in a 0.13-um CMOS process technology. The measurement results indicated that, while the conventional LCD driver If entered latch-up mode at $50^{\circ}C$ accompanying a significant amount of excess current, the driver IC adopting the proposed method showed no latch-up phenomenon up to $100^{\circ}C$ and maintained normal current level of 0.9mA.