• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.4
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• pp.64-71
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• 2009

This paper presents an efficient frame synchronizer architecture using the common autocorrelator for Digital Video Broadcasting via Satellite, Second generation(DVB-S2). To achieve the satisfactory performance under severe channel conditions and the efficient hardware resource utilization of functional synchronization blocks which have been implemented, we propose a new efficient common autocorrelator structure. The proposed architecture can improve the performance of the frame and frequency synchronizer since each block operates jointly in parallel and significantly reduce the complexity of the frame synchronizer. Hence, The proposed architecture can ensure the decrease by about 92% multipliers and 81% adders compared with the direct implementation. Moreover, it has been thoroughly verified with an FPGA board and R&STM SFU broadcast test equipment and consists of 29,821 LUTs with XilinxTM Virtex IV LX200.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.3 s.333
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• pp.39-44
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• 2005

The OFDM modulation and transmission block have been modeled in order to analyse the relationship between the 2.4GHz power amplifier distortion and output ACPR for the IEEE 802.11g wireless LAN. The nonlinear characteristic of the power amplifier has been modeled as AM-to-AM and AM-to-PM using the behavioral model, and the output spectrum is analysed with the phase distortion variation. Also, amplifier back-off value from P1dB to satisfy the required IEEE 802.11g standard spectrum mask s been simulated with modeled phase distortion, and the simulation data have been compared to the measured result by using the pre-distortion technique.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.86-95
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• 2009

SIFT is an algorithm to extract vectors at pixels around keypoints, in which the pixel colors are very different from neighbors, such as vertices and edges of an object. The SIFT algorithm is being actively researched for various image processing applications including 3D image reconstructions and intelligent vision system for robots. In this paper, we implement a hardware to sift feature detection algorithm for real time processing in embedded systems. We estimate that the hardware implementation give a performance 25ms of $1,280{\times}960$ image and 5ms of $640{\times}480$ image at 100MHz. And the implemented hardware consumes 45,792 LUTs(85%) with Synplify 8.li synthesis tool.

• Journal of IKEEE
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• v.19 no.1
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• pp.10-17
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• 2015

In this Paper, an efficient method of FPGA based design and implementation of Sobel Edge detector block using 3-Line buffers is presented. The FPGA provides the proper and sufficient hardware for image processing algorithms with flexibility to support Sobel edge detection algorithm. A pipe-lined method is used to implement the edge detector. The proposed Sobel edge detection operator is an model using of Finite State Machine(FSM) which executes a matrix mask operation to determine the level of edge intensity through different of pixels on an image. This approach is useful to improve the system performance by taking advantage of efficient look up tables, flip-flop resources on target device. The proposed Sobel detector using 3-line buffers is synthesized with Xilinx ISE 14.2 and implemented on Virtex II xc2vp-30-7-FF896 FPGA device. Using matlab, we show better PSNR performance of proposed design in terms of 3-Line buffers utilization.

• Journal of IKEEE
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• v.14 no.1
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• pp.1-7
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• 2010

This paper presents an implementation of the DisplayPort AUX(Auxiliary) Channel. DisplayPort uses Main link, AUX Channel and Hot Plug Detect line to transfer the video & audio data. For isochronous transport service, source device converts to image and audio data which are to be transported through the Main Link and transports the restructured image and audio data to sink device. The AUX Channel provides link service and device service for discovering, initializing and maintaining the Main link. Hot Plug Detect line is used to confirm the connection between source device and sink device. The AUX Channel is implemented with 3315 LUTs(Look Up Table), 1466 Flip Flops and 168.782MHz max speed synthesized using Xilinx ISE 9.2i at SoC Master3.

• Journal of Electrical Engineering and Technology
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• v.11 no.3
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• pp.609-617
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• 2016

Belt-driven Starter Generator (BSG) differs from other mild hybrid systems as the crankshaft of vehicle are not run off. Motor permits a low-cost method of adding mild hybrid capabilities such as start-stop, power assist, and mild levels of regenerative braking. Wound rotor synchronous motor (WRSM) could be adopted in BSG system for HEV e-Assisted application instead of the interior permanent magnet synchronous motor (IPMSM). In practice, adequate torque is indispensable for starter assist system, and energy conversion should be taken into account for the HEV or EV as well. Particularly, flux weakening control is possible to realize by adjusting both direct axis components of current and field current in WRSM. Accordingly, this paper present an off-line current acquisition algorithm that can reasonably combine the stator and field current to acquire the maximum torque, meanwhile the energy conversion is taken into consideration by losses. Besides, on account of inductance influence by non-uniform air gap around rotor, nonlinear inductances and armature flux linkage against current variation are proposed to guarantee the results closer to reality. A computer-aided method for proposed algorithm are present and results are given in form of the Look-up table (LUT). The experiment shows the validity of algorithm.

• Journal of IKEEE
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• v.24 no.3
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• pp.797-802
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• 2020

In this paper, we presents the design and implementation results of the FFT processor, which supports 4096 points of operation with less memory by sharing several memory used in the base-4 systolic array FFT processor into one memory. Sharing memory provides the advantage of reducing the area, and also simplifies the flow of data as I/O of the data progresses in one memory. The presented FFT processor was implemented and verified on the FPGA device. The implementation resulted in 51,855 CLB LUTs, 29,712 CLB registers, 8 block RAM tiles and 450 DSPs, and confirmed that the memory area could be reduced by 65% compared to the existing base-4 systolic array structure.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.41 no.12
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• pp.1844-1850
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• 2016

The bilateral filter can reduce the noise while preserving details computing the filtering output at each pixels as the average of neighboring pixels. In this paper, we propose a real-time system based on window division. Overall performance is increased due to the parallel architectures which computes five rows in the kernel window simultaneously but with pipelined scheduling. We consider the tradeoff between the filter performance and the hardware cost and the bit allocation has been determined by PSNR analysis. The proposed architecture is designed with verilogHDL and synthesized using Dongbu Hitek 110nm standard cell library. The proposed architecture shows 416Mpixels/s (397fps) of throughput at 416MHz of operating frequency with 132K gates.

• Journal of IKEEE
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• v.24 no.1
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• pp.339-346
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• 2020

In this paper, we propose an angle estimator that is designed to be applied to Bluetooth low-power application technology based on multiple signal classification (MUSIC) algorithm, and present the result of implementation in FPGA. The MUSIC algorithm is designed for H/W high-speed design because it requires a lot of calculations due to high accuracy, and the snapshot variable is designed to cope with various resolution requirements of indoor systems. As a result of the implementation with Xilinx zynq-7000, it was confirmed that 9,081 LUTs were implemented, and it was designed to operate at =the operating frequency of 100MHz.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.895-898
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• 2005

This paper describes a design of LNS-based divider and square-root circuits which are key arithmetic units in graphic processor and digital signal processor. To achive area-efficient and low-power that is an essential consideration for mobile environment, a fixed-point format of 16.16 is adopted instead of conventional floating-point format. The designed divider and square-root units consist of binary-to-logarithm converter, subtractor, logarithm-to-binary converter. The binary to logarithm converter is designed using combinational logic based on six regions approximation method. As a result, gate count reduction is obtained when compared with conventional lookup approack. The designed units is 3,130 gate count and 1,280 gate count. To minimize average percent error 3.8% and 4.2%. error compensation method is employed.