• KSII Transactions on Internet and Information Systems (TIIS)
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• v.6 no.6
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• pp.1718-1734
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• 2012

The proposed method in this paper is derived from Mielikainen's hiding method. However, there exist some significant differences between two methods. In Mielikainen's method, pixels are partitioned into pairs and a LSB matching function is applied to two pixels for hiding. On the contrary, the proposed method partitions pixels into groups with three pixels in each group. The bits of pixels in each group are linked by using an exclusive OR (XOR) operator in a circular way. If the number of different values between the calculated XOR values and the secret bits is smaller than or equal to 2 in a group, the proposed method can guarantee that at most one pixel is needed to be modified by adding/subtracting its value to/from one, and three secret bits can be embedded to three pixels. Through theoretical analysis, the amount of the embedded secret data in the proposed method is larger than those in other methods under the same amount of pixel modifications. Taking real images in our experiments, the quality of stego-images in the proposed method is higher than those in other methods.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.5 no.4
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• pp.840-855
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• 2011

In the context of additive noise steganography model, we propose a method to detect least significant bit (LSB) matching steganography in grayscale images. Images are decomposed into detail sub-bands with local linear transform (LLT) masks which are sensitive to embedding. Novel normalized characteristic function features weighted by a bank of band-pass filters are extracted from the detail sub-bands. A suboptimal feature set is searched by using a threshold selection algorithm. Extensive experiments are performed on four diverse uncompressed image databases. In comparison with other well-known feature sets, the proposed feature set performs the best under most circumstances.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.7 no.10
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• pp.2514-2526
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• 2013

This paper presents a detection method for least significant bit matching revisited (LSBMR) steganography. Previous research shows that the adjacent pixels of natural images are highly correlated and the value 0 appears most frequently in pixel difference. Considering that the message embedding process of LSBMR steganography has a weighted-smoothing effect on the distribution of pixel difference, the frequency of the occurrence of value 0 in pixel difference changes most significantly whereas other values approximately remain unchanged during message embedding. By analyzing the effect of LSBMR steganography on pixel difference distribution, an equation is deduced to estimate the frequency of difference value 0 using the frequencies of difference values 1 and 2. The sum of the ratio of the estimated value to the actual value as well as the ratio of the frequency of difference value 1 to difference value 0 is used as the steganalytic detector. Experimental results show that the proposed method can effectively detect LSBMR steganography and can outperform previous proposed methods.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.4
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• pp.62-68
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• 2010

This work proposes a 10b 100MS/s DAC based on a segmented local matching technique primarily for small chip area. The proposed DAC employing a segmented current-steering structure shows the required high linearity even with the small number of devices and demonstrates a fast settling behavior at resistive loads. The proposed segmented local matching technique reduces the number of current cells to be matched and the size of MOS transistors while a double-cascode topology of current cells achieves a high output impedance even with minimum sized devices. The prototype DAC implemented in a 0.13um CMOS technology occupies a die area of $0.13mm^2$ and drives a $50{\Omega}$ load resistor with a full-scale single output voltage of $1.0V_{p-p}$ at a 3.3V power supply. The measured DNL and INL are within 0.73LSB and 0.76LSB, respectively. The maximum measured SFDR is 58.6dB at a 100MS/s conversion rate.

• Korean Journal of Optics and Photonics
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• v.17 no.2
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• pp.181-185
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• 2006

A novel 60GHz optical carrier generator with a polarization domain-inverted structure is suggested and is demonstrated. The two arms of the Mach-Zehnder optical waveguide are periodically poled for quasi-phase velocity matching between the optical wave at 1550nm and the RF wave at 30 GHz. The center frequency of band-pass modulation and the 3 dB bandwidth of the fabricated modulator were measured to be 30.3 GHz and 5.1 GHz, respectively. Sub-carriers with the frequency difference of 60GHz waeregenerated under appropriate DC biac voltage application while the carrier was suppressed to lead to the power ratio between the modulated sub-carrier and the suppressed fundamental carrier of 28 dB, which proves that double sideband- suppressed carrier(DSB-SC) operation can be realized by the suggested single device.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.55-64
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• 2006

This work proposes a calibration-free 14b 70MS/s 0.13um CMOS ADC for high-performance integrated systems such as WLAN and high-definition video systems simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs signal insensitive 3-D fully symmetric layout techniques in two MDACs for high matching accuracy without any calibration. A three-stage pipeline architecture minimizes power consumption and chip area at the target resolution and sampling rate. The input SHA with a controlled trans-conductance ratio of two amplifier stages simultaneously achieves high gain and high phase margin with gate-bootstrapped sampling switches for 14b input accuracy at the Nyquist frequency. A back-end sub-ranging flash ADC with open-loop offset cancellation and interpolation achieves 6b accuracy at 70MS/s. Low-noise current and voltage references are employed on chip with optional off-chip reference voltages. The prototype ADC implemented in a 0.13um CMOS is based on a 0.35um minimum channel length for 2.5V applications. The measured DNL and INL are within 0.65LSB and l.80LSB, respectively. The prototype ADC shows maximum SNDR and SFDR of 66dB and 81dB and a power consumption of 235mW at 70MS/s. The active die area is $3.3mm^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.1-11
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• 2008

This work proposes a 15b 50MS/s CMOS pipeline ADC based on digital code-error calibration. The proposed ADC adopts a four-stage pipeline architecture to minimize power consumption and die area and employs a digital calibration technique in the front-end stage MDAC without any modification of critical analog circuits. The front-end MDAC code errors due to device mismatch are measured by un-calibrated back-end three stages and stored in memory. During normal conversion, the stored code errors are recalled for code-error calibration in the digital domain. The signal insensitive 3-D fully symmetric layout technique in three MDACs is employed to achieve a high matching accuracy and to measure the mismatch error of the front-end stage more exactly. The prototype ADC in a 0.18um CMOS process demonstrates a measured DNL and INL within 0.78LSB and 3.28LSB. The ADC, with an active die area of $4.2mm^2$, shows a maximum SNDR and SFDR of 67.2dB and 79.5dB, respectively, and a power consumption of 225mW at 2.5V and 50MS/s.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.15 no.3
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• pp.1051-1077
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• 2021

The secure communication of information is a major concern over the internet. The information must be protected before transmitting over a communication channel to avoid security violations. In this paper, a new hybrid method called compressed encrypted data embedding (CEDE) is proposed. In CEDE, the secret information is first compressed with Lempel Ziv Welch (LZW) compression algorithm. Then, the compressed secret information is encrypted using the Advanced Encryption Standard (AES) symmetric block cipher. In the last step, the encrypted information is embedded into an image of size 512 × 512 pixels by using image steganography. In the steganographic technique, the compressed and encrypted secret data bits are divided into pairs of two bits and pixels of the cover image are also arranged in four pairs. The four pairs of secret data are compared with the respective four pairs of each cover pixel which leads to sixteen possibilities of matching in between secret data pairs and pairs of cover pixels. The least significant bits (LSBs) of current and imminent pixels are modified according to the matching case number. The proposed technique provides double-folded security and the results show that stego image carries a high capacity of secret data with adequate peak signal to noise ratio (PSNR) and lower mean square error (MSE) when compared with existing methods in the literature.

• The Bulletin of The Korean Astronomical Society
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• v.46 no.1
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• pp.29.2-29.2
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• 2021

Intracluster light (ICL) is composed of the stars diffused throughout the galaxy cluster but does not bound to any galaxy. The ICL is a ubiquitous feature of galaxy clusters and occupies a significant fraction of the total stellar mass in the cluster. Therefore, the ICL components are believed to help understand the formation and evolution of the clusters. However, in the numerical study, one needs to perform the high-resolution cosmological hydrodynamic simulations, which require an expensive calculation, to trace these low-surface brightness structures (LSB). Here, we introduce the Galaxy Replacement Technique (GRT) that focuses on implementing the gravitational evolution of the diffused ICL structures without the expensive baryonic physics. The GRT reproduces the ICL structures by a multi-resolution cosmological N-body re-simulation using a full merger tree of the cluster from a low-resolution DM-only cosmological simulation and an abundance matching model. Using the GRT, we show the preliminary results about the evolution of the ICL in the on-going simulations for the various clusters.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.6 no.8
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• pp.1926-1945
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• 2012

In this paper, two practical forensics aided steganalyzers (FA-steganalyzer) for heterogeneous bitmap images are constructed, which can properly handle steganalysis problems for mixed image sources consisting of raw uncompressed images and JPEG decompressed images with different quality factors. The first FA-steganalyzer consists of a JPEG decompressed image identifier followed by two corresponding steganalyzers, one of which is used to deal with uncompressed images and the other is used for mixed JPEG decompressed images with different quality factors. In the second FA-steganalyzer scheme, we further estimate the quality factors for JPEG decompressed images, and then steganalyzers trained on the corresponding quality factors are used. Extensive experimental results show that the proposed two FA-steganalyzers outperform the existing steganalyzer that is trained on a mixed dataset. Additionally, in our proposed FA-steganalyzer scheme, we can select the steganalysis methods specially designed for raw uncompressed images and JPEG decompressed images respectively, which can achieve much more reliable detection accuracy than adopting the identical steganalysis method regardless of the type of cover source.