• KSII Transactions on Internet and Information Systems (TIIS)
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• v.12 no.10
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• pp.4754-4773
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• 2018

In sensor medium access control (SMAC) protocol, sensor nodes can only access the channel in the scheduling and listening period. However, this fixed working method may generate data latency and high conflict. To solve those problems, scheduling duty in the original SMAC protocol is divided into multiple small scheduling duties (micro duty MD). By applying different micro-dispersed contention channel, sensor nodes can reduce the collision probability of the data and thereby save energy. Based on the given micro-duty, this paper presents an adaptive duty cycle (DC) and back-off algorithm, aiming at detecting the fixed duty cycle in SMAC protocol. According to the given buffer queue length, sensor nodes dynamically change the duty cycle. In the context of low duty cycle and low flow, fair binary exponential back-off (F-BEB) algorithm is applied to reduce data latency. In the context of high duty cycle and high flow, capture avoidance binary exponential back-off (CA-BEB) algorithm is used to further reduce the conflict probability for saving energy consumption. Based on the above two contexts, we propose an improved SMAC protocol, micro duty adaptive SMAC protocol (MDA-SMAC). Comparing the performance between MDA-SMAC protocol and SMAC protocol on the NS-2 simulation platform, the results show that, MDA-SMAC protocol performs better in terms of energy consumption, latency and effective throughput than SMAC protocol, especially in the condition of more crowded network traffic and more sensor nodes.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.6
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• pp.459-468
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• 2003

This paper proposes a novel low-cost and high-speed Reed-Solomon (RS) decoder based on a new degree computationless modified Euclid´s (DCME) algorithm. This architecture has quite low hardware complexity compared with conventional modified Euclid´s (ME) architectures, since it can remove completely the degree computation and comparison circuits. The architecture employing a systolic away requires only the latency of 2t clock cycles to solve the key equation without initial latency. In addition, the DCME architecture using 3t＋2 basic cells has regularity and scalability since it uses only one processing element. The RS decoder has been synthesized using the 0.25${\mu}{\textrm}{m}$. Faraday CMOS standard cell library and operates at 200MHz and its data rate suppots up to 1.6Gbps. For tile (255, 239, 8) RS code, the gate counts of the DCME architecture and the whole RS decoder excluding FIFO memory are only 21,760 and 42,213, respectively. The proposed RS decoder can reduce the total fate count at least 23% and the total latency at least 10% compared with conventional ME architectures.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.8
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• pp.40-48
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• 2015

This paper presents a processor that performs QR decomposition (QRD) as well as Lattice Reduction (LR) for multiple-input multiple-output (MIMO) systems. By sharing the operations commonly required in QRD and LR, the hardware complexity of the proposed processor is reduced significantly. In addition, the proposed processor is designed based on a multi-cycle architecture so as to reduce the hardware complexity. The proposed processor is implemented with 139k logic gates in a $0.18-{\mu}m$ CMOS process, and its latency is $5{\mu}s$ for $8{\times}8$ MIMO preprocessing both QRD and LR where the operating frequency is 117MHz.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.2
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• pp.62-68
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• 2007

This paper proposes an efficient integer division algorithm for high speed FPGAs' which support built-in RAMs' and multipliers. The integer division algorithm is iterative with RAM-based LUT and multipliers, which minimizes the usage of logic fabric and connection resources. Compared with some popular division algorithms such as division by subtraction or division by multiply-subtraction, the number of iteration is much smaller, so that very low latency can be achieved with pipelined implementations. We have implemented our algorithm in the Xilinx virtex-4 FPGA with VHDL coding and have achieved 300MSPS data rate in 17bit integer division. The algorithm used less than 1/6 of logic slices, 1/4 of the built-in multiply-accumulation units, and 1/3 of the latencies compared with other popular algorithms.

• Journal of Life Science
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• v.12 no.4
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• pp.375-382
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• 2002

The purpose of this experiment was to examine influence of acute exercise on nocturnal sleep which had been disrupted by caffeine(400mg$\times$3) thought the daytime. Six healthy young males aged 21.0$\times$0.2 yr with a history of low caffeine use. Subjects completed three conditions in a within-subject. At three conditions Sleep EEG were investigated: (1) nocturnal following quiet rest, (2) nocturnal sleep following the consumption of 1200mg of caffeine (3) nocturnal sleep following cycling at 60 min of 60% V $O_{2peak}$ with 1200mg of caffeine consumption. Sleep data were calculated for REM sleep, REM latency, sleep onset latency, sleep efficiency, sleep stages, SWS. Those data were analyzed using repeated-measures ANOVA of change scores. A main effect to, drug(caffeine) indicated that caffeine elicited sleep disturbance that is, TST and sleep onset latency increase and sleep efficiency and stage 4 decrease. The effects of exercise on sleep following caffeine intake generally improve sleep that is, stage 2, 3 and SWS increase and sleep onset latency decrease. A condition effect for sleep indicated sleep improvement after exercise Therefore The data supported a restorative theory of slow-wave sleep and suggest that acute exercise may be useful in promoting sleep and reducing sleep disturbance elevated by a high dose of caffeine.

• Journal of IKEEE
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• v.24 no.2
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• pp.550-558
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• 2020

Successive cancellation (SC) decoding that is one of the decoding algorithms for polar codes has long decoding latency and low throughput because of the nature of successive decoding. To reduce the latency and increase the throughput, various decoding structures for polar codes are presented. In this paper, we compare the previous decoding structures and analyze them by dividing into two types, pruning and multi-path decoders. Decoders for applying pruning are representative of SSC (simplified SC), Fast-SSC and redundant-LLR structures, and decoders with multi-path are representative of 2-bit SC and redundant-LLR structures. All the previous structures are compared in terms decoding latency and hardware area, and according to the comparison, the syndrome check based decoder has the lowest latency and redundant-LLR decoder has the highest hardware efficiency.

• Journal of the Ergonomics Society of Korea
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• v.31 no.6
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• pp.785-791
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• 2012

Objective: The aim of this study was to investigate the correlation between 3D visual fatigue and physiological measures by canonical correlation analysis enabling to categorical correlation. Background: Few studies have been conducted to investigate the physiological mechanism underlying the visual fatigue caused by processing 3D information which may make the cognitive mechanism overloaded. However, even the previous studies lack validation in terms of the correlation between physiological variables and the visual fatigue. Method: 9 Female and 6 male subjects with a mean age of $22.53{\pm}2.55$ voluntarily participated in this experiment. All participants were asked to report how they felt about their health sate at after viewing 3D. In addition, Low & Hybrid measurement test(Event Related Potential, Steady-state Visual Evoked Potential) and for evaluating cognitive fatigue before and after viewing 3D were performed. The physiological signal were measured with subjective fatigue evaluation before and after in watching the 3D content. For this study suggesting categorical correlation, all measures were categorized into three sets such as included Visual Fatigue set(response time, subjective evaluation), Autonomic Nervous System set(PPG frequency, PPG amplitude, HF/LF ratio), Central Nervous System set(ERP amplitude P4, O1, O2, ERP latency P4, O1, O2, SSVEP S/N ratio P4, O1, O2). Then the correlation of three variables sets, canonical correlation analysis was conducted. Results: The results showed a significant correlation between visual fatigue and physiological measures. However, different variables of visual fatigue were highly correlated to respective HF/LF ratio and to ERP latency(O2). Conclusion: Response time was highly correlated to ERP latency(O2) while the subjective evaluation was to HF/LF ratio. Application: This study may provide the most significant variables for the quantitative evaluation of visual fatigue using HF/LF ratio and ERP latency based human performance and subjective fatigue.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.75-78
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• 2007

Mobile IP provides hand-held devices with mobility which allows the user to do work over the network. However, handover time due transfer between access routers causes network delays and data loss. L2Trigger Handover expects this handover to take place, and executes L3 handover before L2 handover takes place, thereby reducing overall handover latency, although it still is an issue since handover latency between AR is not completely eliminated in L2 trigger handover. In this paper took into consideration where MIH is used in MIPv4 and using MIH Table when handover is about to occur in MN(Mobile Node), thereby pre-fetching data needed by Handover. In this way, when the handover is estimated, it improves the init time that L2trigger had. Furthermore we can find that we can execute the handover with shorten init time in smaller and narrow overlap length

• Journal of Internet Computing and Services
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• v.7 no.1
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• pp.121-130
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• 2006

In next generation wireless networks, an application must be capable of rating service information in real-time and prior to initiation of the service it is necessary to check whether the end user's account provides coverage for the requested service. However, to provide prepaid services effectively, credit-control should have minimal latency. In an endeavor to support real-time credit-control for Mobile IPv6 (MIPv6), we design an implementation architecture model of credit-control authorization. The proposed integrated model combines a typical credit-control authorization procedure into the MIPv6 authentication procedure. We implement it on a single server for minimal latency. Thus, the server can perform credit-control authorization and MIPv6 authentication simultaneously. Implementation details are described as software blocks and units. In order to verify the feasibility of the proposed model. latency of credit-control authorization is measured according to various Extensible Authentication Protocol (EAP) authentication mechanisms. The performance results indicate that the proposed approach has considerably low latency compared with the existing separated models, in which credit-control authorization is separated from the MIPv6 authentication.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.12C
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• pp.1207-1214
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• 2002

A scheduling scheme for high speed networks requires a low time complexity to schedule packets in a packet transmission time. High speed networks support a number of connections, different rates for each connection and variable packet length. Conventional round robin algorithms have a time complexity of O(1), but their short time fairness, latency and burstiness depend on the quantum of a connection due to serving several packets for a backlogged connection once a round. To improve these properties, we propose in this paper an efficient packet scheduling scheme which is based on the credits of a connection and has a time complexity of O(1). We also analyzed its performance in terms of short time fairness, latency and burstiness. The analysis results show that the proposed scheme can improve the performance compared with traditional round robin schemes. The proposed scheme can be easily utilized in high speed packet networks.