• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.11
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• pp.65-71
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• 2010

This paper presents a 14-band LO generator architecture for MB-OFDM UWB systems using 3.1 GHz~10.6 GHz frequency band. The proposed LO generator architecture has been consisted of only one PLL and the fewest nonlinear components to generate 14 LO signals with high purity while consuming low dc power consumption. In addition, major spurious generated from the LO generator have been located in the out of UWB band. The proposed LO generator has been implemented in a $0.13-{\mu}m$ CMOS technology and consumes a dc power consumption of 93~103 mW from a 1.5 V supply. The simulation results show an in-band spurious suppression ratio of more than 41 dBc and a band-switching time of below 3 nsec.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.11
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• pp.66-70
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• 2016

This paper presents an 24 GHz I/Q LO generator for a heartbeat measurement radar system. In order to improve the mismatch performance between I and Q LO signals against process variation, a 24 GHz I/Q LO generator employing a low-pass phase shifter and a high-pass phase shifter composed of inductors and capacitors is proposed. The proposed 24 GHz I/Q LO generator consists of an LO buffer, a low-pass phase shifter and a high-pass phase shifter. It was designed using a 65 nm CMOS technology and draws 8 mA from a 1 V supply voltage. The proposed 24 GHz I/Q LO generator shows a gain of 7.5 dB, a noise figure of 2.3 dB, 0.1 dB gain mismatch and $4.3^{\circ}$ phase mismatch between I and Q-path against process and temperature variations for the operating frequencies from 24.05 GHz to 24.25 GHz.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.14 no.1
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• pp.71-77
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• 2004

It was proved that Hen is an algebraic ,elation of degree [n(l+1]/2] for an (n, 1)-combine. which consists of n LFSRs and l memory bits. For the summation generator with $2^k$ LFSRs which uses k memory bits, we show that there is a non-trivial relation of degree at most $2^k$ using k+1 consecutive outputs. In general, for the summation generator with n LFSRs, we can construct a non-trivial algebraic relation of degree at most 2$^{{2^{[${log}_2$}n]}}$ using [${log}_2$＋1 consecutive outputs.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.40 no.5
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• pp.197-203
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• 2003

In this paper, we have presented millimeter-wave high conversion gain quadruple subharmonic mixers adopting the cascode harmonic generator The subharmonic mixers were successfully integrated by using 0.1 ${\mu}{\textrm}{m}$ GaAs pseudomorphic HEMTs(PHEMTs) and coplanar waveguide(CPW) structures. Measured output of 1st, 2nd and 4th harmonics of the fabricated cascode 4th harmonic generator are -21.42 dBm, -32.65 dBm and -13.45 dBm, respectively, for an input power of 10 dBm at 14.5 GHz. We showed that the highest conversion gain of 3.4 dB has obtained thus far at a LO power of 13 dBm from the fabricated subharmonic mixers. The millimeter-wave subharmonic mixer also ensure a high degree of isolation showing -53.6 dB in the LO-to-IF and -46.2 dB in the LO-to-RF, respectively, at a frequency of 14.5 GHz. The high conversion gain achieved in this work is the first report among the millimeter-wave subharmonic mixers.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.18 no.5
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• pp.97-102
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• 2018

In this paper, W-band Waveform Generator for compact radar has been designed and fabricated. DDS (Direct Digital Synthesizer) is applied to generate CW (Continuous Wave) and FMCW (Frequency Modulation Continuous Wave) waveform at high speed. We designed two LO (Local Oscillator) paths for functions of distance delay and distance tracking tests at the prpposed system without extra test equipment. Two mode selections are provided by switch. It is observed that fabricated waveform generator performs -91 dBc/Hz phase noise at offset 1 kHz and -63.2 dBc spurious. Proposed W-band Waveform Generator is expected to apply for W-band compact radar transceiver module.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.5 s.335
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• pp.55-60
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• 2005

A V-band MIMIC quadruple subharmonic mixer is reported in this paper. The cascode harmonic generator is proposed for a high conversion gain. The proposed cascode harmonic generator is shown with a 4-th harmonic output characteristic that represents an average of 2.9 dB and a maximum of 4 dB higher than the conventional multiplier. The measured result of the subharmonic mixer has a conversion gain of 3_4 dB which a good conversion gain at a LO power of 13 dBm. Isolations of LO-to-IF and LO-to-RF were obtained -53.6 dB and -46.2 dB, respectively. The conversion gain of the subharmonic mixer in this study has a higher conversion gain compared with some other reports in millimeter-wave range.

• Journal of electromagnetic engineering and science
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• v.6 no.1
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• pp.18-23
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• 2006

In this paper, we demonstrate a fully integrated X-band image rejection down converter, which was developed using InGaP/GaAs HBT MMIC technology, consists of two single-balanced mixers, a differential buffer amplifier, a differential YCO, an LO quadratue generator, a three-stage polyphase filter, and a differential intermediate frequency(IF) amplifier. The X-band image rejection downconverter yields an image rejection ratio of over 25 dB, a conversion gain of over 2.5 dB, and an output-referred 1-dB compression power$(P_{1dB,OUT})$ of - 10 dBm. This downconverter achieves broadband image rejection characteristics over a frequency range of 1.1 GHz with a current consumption of 60 mA from a 3-V supply.

• Proceedings of the Korean Society of Propulsion Engineers Conference
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• 2011.04a
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• pp.93-96
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• 2011

A genetic algorithm (GA) has been employed to optimize the major design variables of the liquid rocket engine. Mass flow rate to the main thrust chamber, mass flow rate to the gas generator and chamber pressure have been selected as design variables. The target engine is the open gas generator cycle using the LO2/RP-1 propellant. The objective function of design optimization is to maximize the specific impulse with condition of energy balance between the pump and the turbine. The properties of the combustion chamber have been obtained from CEA2. Pump & turbine efficiencies and properties of the gas generator have been modeled mathematically from reference data. The result shows 3~4% errors for the specific impulse and 2~6% errors for the pump power of the gas generator cycle compared to references.

• ETRI Journal
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• v.36 no.6
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• pp.924-930
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• 2014

This paper presents a $0.13{\mu}m$ CMOS 3-level envelope delta-sigma modulation (EDSM) RF signal generator, which synthesizes a 2.6 GHz-centered fully symmetrical 3-level EDSM signal for high-efficiency power amplifier architectures. It consists of an I-Q phase modulator, a Class B wideband buffer, an up-conversion mixer, a D2S, and a Class AB wideband drive amplifier. To preserve fast phase transition in the 3-state envelope level, the wideband buffer has an RLC load and the driver amplifier uses a second-order BPF as its load to provide enough bandwidth. To achieve an accurate 3-state envelope level in the up-mixer output, the LO bias level is optimized. The I-Q phase modulator adopts a modified quadrature passive mixer topology and mitigates the I-Q crosstalk problem using a 50% duty cycle in LO clocks. The fabricated chip provides an average output power of -1.5 dBm and an error vector magnitude (EVM) of 3.89% for 3GPP LTE 64 QAM input signals with a channel bandwidth of 10/20 MHz, as well as consuming 60 mW for both channels from a 1.2 V/2.5 V supply voltage.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.9
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• pp.74-80
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• 2009

This paper describes a $2{\sim}6GHz$ CMOS frequency synthesizer that employs only one LC-tank voltage controlled oscillator (VCO). For wide-band operation, optimized LO signal generator is used. The LC-tank VCO oscillating in $6{\sim}8GHz$ provides the required LO frequency by dividing and mixing the VCO output clocks appropriately. The frequency synthesizer is based on a fractional-N phase locked loop (PLL) employing third-order 1-1-1 MASH type sigma-delta modulator. Implemented in a $0.18{\mu}m$ CMOS technology, the frequency synthesizer occupies the area of $0.92mm^2$ with of-chip loop filter and consumes 36mW from a 1.8V supply. The PLL is completed in less than $8{\mu}s$. The phase noise is -110dBC/Hz at 1MHz offset from the carrier.