• ETRI Journal
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• v.24 no.4
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• pp.328-331
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• 2002

We investigated the electrical characteristics of p-channel double-diffused MOSFETs (p-LDMOSFETs) with an uneven racetrack source (URS) and a conventional racetrack source (CRS) for PDP driver IC applications. The breakdown voltage of the p-LDMOSFET with the URS in offstate was nearly the same as the p-LDMOSFET with the CRS. However, the breakdown voltage of the p-LDMOSFET with the URS in on-state was about 30% higher than that of the p-LDMOSFET with the CRS, while the saturated drain current of the p-LDMOSFET with the URS was only about 4% lower than that of the p-LDMOSFET with the CRS.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.695-698
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• 2003

This paper presents a Si power LDMOSFET for power amplifiers in the 1.8-2.2GHz frequency range for the base station of personal communication systems. To improve the cut-off frequency, the proposed Si power LDMOSFET has small gate to drain capacitance by shielding the electric fields with extended source electrode and forming the field oxide structure in drain region. The proposed Si power LDMOSFET can be used for a power amplifier and it has 32% of power added efficiency and 39.5dBm of output power when the supply voltage is 28V and the operating frequency is 1.9GHz.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.11-12
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• 2005

2 차원 MEDICI 시뮬레이터를 이용하여 CMOS 회로의 전기적 특성을 조사하였다. CMOS 인버터 회로는 LDMOSFET를 이용하였는데, LDMOSFET에서 전류 및 스위칭 특성에 많은 영향을 주는 곳은 채널이라고 생각되는데, 채널에서의 불순물 농도 변화에 의한 CMOS 회로의 voltage transfer특성, low input voltage($V_{IL}$), high input voltage($V_{IH}$)등을 조사하였다. LDMOSFET에서 N 채널의 농도는 $V_{IL}$에, P 채널의 농도는 $V_{IH}$에 많은 영향을 주었다.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.355-358
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• 2004

In this work, N-LDMOSFET(Lateral Double diffused MOSFET) was designed and fabricated on SOI(Silicon-On-Insulator) substrate, for such applications as motor controllers and high voltage switches, fuel injection controller systems in automobile and SSR(Solid State Rexay)etc. The LDMOSFET was designed to overcome the floating body effects that appear in the conventional thick SOI MOS structure by adding p+ region in source region. Also, RESURF(Reduced SURface Field) structure was proposed in this work in order to reduce a large on-resistance of LDMOSFET when operated keeping high break down voltage. Breakdown voltage was 268v in off-state ($V_{GS}$=OV) at room temperature in $22{\mu}m$ drift length LDMOSFET. When 5V of $V_{GS}$ and 30V of $V_{DS}$ applied, the on resistance(Ron), the transcon ductance($G_m$) and the threshold voltage($V_T$) was 1.76k$\Omega$, 79.7uA/V and 1.85V respectively.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.1
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• pp.23-28
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• 2006

In this paper, breakdown voltage and on-resistance characteristics of the surface doped SOI RESURF LDMOSFET were investigated as a function of surface doping depth. In order to verify the variation of characteristics, two-dimensional device simulation was carried out. Breakdown voltage of the proposed structure is varied from $73 {\~}138V$ while surface doping depth varied from $0.5{\~}2.0{\mu}m$. And on-resistance is decreased from $0.18{\~}0.143{\Omega}/cm^2$ while surface doping depth increased from $0.5 {\~}2.0{\mu}m$. Maximum breakdown voltage of the proposed structure is 138 V at $1.5{\mu}m$ depth of surface doping, yielding $22.1\%$ of improvement of breakdown voltage in comparison with that of the conventional SOI RESURF LDMOSFET with same epi-layer concentration. On-resistance characteristic is also improved about $21.7\%$.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.234-237
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• 2000

In this paper, a method to implement new Quasi-SOI LDMOSFET is introduced and the electrical characteristics of the device are studied. Key process steps of the device are explained briefly. By performing process and device simulations, electrical characteristics of the device are investigated, with emphasis on the optimization of the tilt angle of p$\^$0/ channel region. The electrical properties of the Quasi-SOI device are compared with those of bulk and SOI devices with the same process parameters. Simulated device characteristics are threshold voltage, off-state leakage current, subthreshold swing, DIBL, output resistance, lattice temperature, I$\_$D/-V$\_$Ds/, and cut-off frequency.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.201-204
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• 2001

LDMOSFET devices operated at low temperature have applications on satellite, space shuttle and low temperature system, etc. In this study, we measured the electrical characteristics of 100v Class LDMOSFET for low temperature application. Measurement data are taken over a wide range of temperatures (100K-300K) and various drift region lengths(6.6${\mu}{\textrm}{m}$, 8.4${\mu}{\textrm}{m}$, 12.6${\mu}{\textrm}{m}$). Maximum transconductance, $g_{m}$ and drain current at low temperatures(~100K) increased over about 260%, 50% respectively, in comparison with the data at room temperature. Breakdown voltage B $V_{ds}$, and specific on- resistance decreased. Besides, ratio $R_{on}$ BV, a figure of merit of the device, decreased with decreasing temperature.

• Transactions on Electrical and Electronic Materials
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• v.7 no.3
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• pp.99-102
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• 2006

The electrical characteristics of CMOS inverter with LDMOSFET are studied for high power and digital circuit application by using two dimensional MEDICI simulator. The simulation is done in terms of voltage transfer characteristic and on-off switching properties of CMOS inverter with variation of channel length and channel doping levels. The channel which surrounds a junction-type source in LDMOSFET is considered to be an important parameter to decide a circuit operation of CMOS inverter. The digital logic levels of input voltage show to increase with increase of n-channel length and doping levels while the logic output levels show to the almost constant.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.101-102
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• 2005

SiC lateral power semiconductor device has high breakdown voltage and low on-state voltage drop due to the material characteristics. And, because the high breakdown voltage can be obtained, RESURF technique is mostly used in silicon power semiconductor devices. In this paper, we presents the electrical characteristics of the 4H-SiC RESURF LDMOSFET as a function of the epi-layer length, concentration and thickness. 240~780V of breakdown voltage can be obtained as a function of epi-layer length and thickness with same epi-layer concentration.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.201-202
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• 2005

The electrical characteristics of high-voltage LDMOSFET (Lateral Double-diffused MOSFET) fabricated by a CMOS technology were investigated depending on the process and design parameters. The off-state breakdown voltages of n-channel LDMOSFETs were linearly increased with increasing to the drift region length. For the case of decreasing n-well ion implant doses from $1.0\times10^{13}/cm^2$ to $1.0\times10^{12}/cm^2$, the off-state breakdown voltage was increased approximately two times, however, the on-resistance was also increased about 76%. Moreover, the on- and off-state breakdown voltages were also linearly increased with increasing the channel to n-tub spacing due to the reduction of impact ionization at the drift region.