• 전자공학회논문지A
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• 제33A권2호
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• pp.131-139
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• 1996

Inthis apper wa analyzed the channel-hot-electron programming characteristics of the single-poly EEPROM with different control gate and drain structures. The single-poly EEPROM uses the p$^{+}$/n$^{+}$-diffusion in the n-well as a control gate instead of the second poly-silicon. The program and erase characteristics of the single-poly EEPROM were verified using the two-dimensional device simulator, MEDICI. The single-poly EEPROM was fabricated using 0.8$\mu$m ASIC CMOS process, and its CHE programming characteristics were measured using HP4155 parameteric analyzer and HP8110 pulse gnerator. Especially we investigated the CHE programming characteristics of the single-poly EEPROM with the p$^{+}$-diffusion or n$^{+}$-diffusion in the n-well as a control gate and the LDD or single-drain structure. The single-poly EEPROM with p$^{+}$-diffusion in the n-well as a control gate and single-drain structure was programmed to about VT$\thickapprox$5V with VDS=6V, VCG=12V(1ms pulse width).th).

• 전자공학회논문지A
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• 제30A권12호
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• pp.60-68
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• 1993

Thw VLSI device of submicron level trends to have a low level of reliability because of hot carriers which are caused by short channel effects and which do not appear in a long-channel MOSFET operated in 5V. In order to minimize the generation of hot carrier, much research has been made into various types of drain structures. This study has suggested CG MOSFET (Concaved Gate MOSFET) as new drain structure and compared its electrical characteristics with those of the conventional MOSFET and LDD-structured MOSFET by making use of a simulation method. These three device were assumed to be produced by the LOCOS process and a computer-based analysis(PISCES-2B simulator) was carried out to verify the hot electron-resistant behaviours of the devices. In the present simulation, the channel length of these devises was 1.0$\mu$m and their DC characteristics, such as VS1DT-IS1DT curves, gate and substrate current, potential contours, breakdown voltage and electric field were compared with one another.

• Transactions on Electrical and Electronic Materials
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• 제7권1호
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• pp.1-6
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• 2006

Hot carrier degradation and roll off characteristics of threshold voltage ($V_{t1}$) on NMOSFETs as I/O transistor are studied as a function of Lightly Doped Drain (LDD) structures. Pocket dose and the combination of Phosphorus (P) and Arsenic (As) dose are applied to control $V_{t1}$ roll off down to the $10\%$ gate length margin. It was seen that the relationship between $V_{t1}$ roll off characteristic and substrate current depends on P dopant dose. For the first time, we found that the n-p-n transistor triggering voltage ($V_{t1}$) depends on drain current, and both $I_{t2}$ and snapback holding voltage ($V_{sp}$) depend on the substrate current by characterization with a transmission line pulse generator. Also it was found that the improved lifetime for hot carrier stress could be obtained by controlling the P dose as loosing the $V_{t1}$ roll off margin. This study suggests that the trade-off characteristic between gate length margin and channel hot carrier (CHC) lifetime in NMOSFETs should be determined by considering Electrostatic Discharge (ESD) characteristic.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2008년도 춘계종합학술대회 A
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• pp.105-110
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• 2008

식각 형상비에 의해 경사형 스페이스를 갖는 도핑 산화막을 이용한 LDD 영역을 갖도록 제작한 다결정 TFT의 새로운 구조를 제안한다. 소자 특성의 신뢰성을 위해 수소($H_2$)와 수소/플라즈마 처리 공정으로 다결정 실리콘에 수소 처리시킨 n-채널 다결정 실리콘 TFT 소자를 제작하였다. 소자에 최대 누설전류의 게이트 전압 조건에서 소자에 스트레스를 인가시켰다. 게이트 전압 스트레스 조건에 의해 야기되는 열화 특성인자들은 드레인 전류, 문턱전압($V_{th}$), 부-문턱전압 기울기(S), 최대 전달 컨덕턴스($g_m$), 그리고 파워인자 값을 측정/추출하였으며, 수소처리 공정이 소자 특성의 열화 결과에 미치는 관계를 분석하였다. 특성 파라미터의 분석 결과로써, 수소화 처리시킨 n-채널 다결정 실리콘 박막 트랜지스터에서 열화특성의 원인들은 다결정 실리콘/산화막의 계면과 다결정 실리콘의 그레인 경계에서 실리콘-수소 본드의 해리에 의한 현수 본드의 증가이었다. 이 증가가 소자의 핫-캐리어와 결합으로 개선된 열화 특성의 원인이 되었다. 따라서 새로 제안한 다결정 TFT의 구조는 제작 공정 단계가 간단하며, 소자 특성에서 누설전류가 드레인 영역 근처 감소된 수평 전계에 의해 감소되었다.

• Journal of Electrical Engineering and information Science
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• 제3권2호
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• pp.261-266
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• 1998

This paper describes the fabrication and characterization of dual-polysilicon gated surface channel 0.1$\mu\textrm{m}$ CMOSFETs using BF2 and arsenic as channel dopants. We have used and LDD structure and 40${\AA}$ gate oxide as an insulator. To suppress short channel effects down to 0.1$\mu\textrm{m}$ channel length, shallow source/drain extensions implemented by low energy implantation and SSR(Super Steep Retrograde) channel structure were used. The threshold voltages of fabricated CMOSFETs are 0.6V. The maximum transconductance of nMOSFET is 315${\mu}$S/$\mu\textrm{m}$, and that of pMOSFET is 156 ${\mu}$S/$\mu\textrm{m}$. The drain saturation current of 418 ${\mu}$A/$\mu\textrm{m}$, 187${\mu}$A/$\mu\textrm{m}$ are obtained. Subthreshold swing is 85mV/dec and 88mV/dec, respectively. DIBL(Drain Induced Barrier Lowering) is below 100mV. In the device with 2000${\AA}$ thick gate polysilicon, depletion in polysilicon near the gate oxide results in an increase of equivalent gate oxide thickness and degradation of device characteristics. The gate delay time is measured to be 336psec at operation voltage of 2V.

• 한국컴퓨터정보학회논문지
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• 제9권1호
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• pp.9-15
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• 2004

본 논문에서는 드레인 부근의 채널 영역에서 접합 전계를 줄이는 WSW(Wrap Side Wall) 구조의 소자를 제안하였다. WSW구조의 소자 제작은 첫 번째 게이트를 식각한 후에 NM1(N-type Minor1) 이 온주입을 하고 다시 질화막을 덮어 식각함으로서 만들어진다. 새로운 WSW구조는 전계를 줄이기 위한 버퍼층으로 되어 있으며 WSW소자와 LDD구조의 소자 수명을 비교하였으며 핫-캐리어 열화 특성도 분석하였다. 또한 AC 핫-캐리어 열화를 칩 상에서 평가하기 위해 펄스 발생기, 레벨 시프터, 주파수 분배기를 포함한 테스트 패턴 회로를 설계하였다. 이러한 것은 AC와 DC 스트레스간의 핫-캐리어 열화 조건이 AC와 DC 스트레스 모두 동일한 물리적 메커니즘을 지닌다는 것을 알 수 있었다. 따라서 일반적으로 회로 동작 조건 하에서 DC 핫-캐리어 열화 특성을 토대로 AC 소자 수명도 예측할 수 있었다.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제48권12호
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• pp.761-767
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• 1999

Poly-Si TFTs(polycrystalline silicon thin film transistors) fabricated on a low cost glass substrate have attracted a considerable amount of attention for pixel elements and peripheral driving circuits in AMLCS(active matrix liquid crystal display). In order to apply poly-Si TFTs for high resolution AMLCD, a high operating frequency and reliable circuit performances are desired. A new poly-Si TFT with CLBT(counter doped lateral body terminal) is proposed and fabricated to suppress kink effects and to improve the device stability. And this proposed device with BC(buried channel) is fabricated to increase ON-current and operating frequency. Although the troublesome LDD structure is not used in the proposed device, a low OFF-current is successfully obtained by removing the minority carrier through the CLBT. We have measured the dynamic properties of the poly-Si TFT device and its circuit. The reliability of the TFTs and their circuits after AC stress are also discussed in our paper. Our experimental results show that the BC enables the device to have high mobility and switching frequency (33MHz at $V_{DD}$ = 15 V). The minority carrier elimination of the CLBT suppresses kink effects and makes for superb dynamic reliability of the CMOS circuit. We have analyzed the mechanism in order to see why the ring oscillators do not operate by analyzing AC stressed device characteristics.