• Journal of Institute of Control, Robotics and Systems
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• v.7 no.11
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• pp.939-943
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• 2001

PLC(programmable Logic Controller)s essential components of modern automation systems encompassing almost every industry. Ladder Diagrams (LD) have been widely used in the design of such PLC since the LD is suitable for the modeling of the sequential control system. However, the synthesis of LD itself mainly depends on the experience of the industrial engineer, which may results in unstructured or inflexible design. Hence, in this paper, we propose a ladder diagram conversion algorithm which systematically produces LDs for PLCs based on discrete event models to enhance the structured and flexible design mechanism.

• 제어로봇시스템학회:학술대회논문집
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• 2001.10a
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• pp.124.4-124
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• 2001

It needs a skillful experience to design and implement sequential circuits with a relay circuit or LD (Ladder Diagram). One makes out the operation of relay contacts sequentially in case of analyzing a relay circuit or LD. Still more, the design and analyzing of a complex relay circuit or LD are difficult. In this paper, we propose the EMFG (Extended Mark Graph) representation on relay circuits and LD.

• Journal of KIISE:Software and Applications
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• v.37 no.1
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• pp.54-59
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• 2010

Special-purpose microcontrollers PLCs have been widely used in the area of industrial automation. For the research of analysis and verification for PLC programs, first of all we have to specify formal sematics of PLC programming languages. This paper defines formally the operational semantics of LD language. After we transform the graphical language LD into its textual representation Symbolic LD, we give semantics of Symbolic LD since LD language is a graphical language. This paper defines the natural sematics of Symbolic LD and formalizes it in Coq proof assistant.

• Proceedings of the KIEE Conference
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• 1999.07b
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• pp.699-702
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• 1999

This paper represents the application of a virtual plant simulator and a Ladder Diagram of PLC. A target plant is a material transport car that repeatedly conveys along the rails. The whole process is automatically operated by PLC. The simulation system consists of the POSFA PLC and the virtual plant simulator. We demonstrate that operation of a LD program corresponds to operation of the virtual plant simulator.

• Journal of Institute of Control, Robotics and Systems
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• v.5 no.1
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• pp.33-38
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• 1999

This paper proposes a translation approach for PLCs (Programmable logic controllers) converting ladder diagrams directly to native codes, and describes detailed steps of the method followed by performance evaluation. A general-purpose DSP (Digital signal processor) based implementation validates the approach as well. A benchmark test shows that the Proposed translation framework fairly speeds up execution in comparison with the existing interpretation approach.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.20 no.4
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• pp.49-55
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• 2006

In industrial control system used by Programmable Logic Controller(PLC), ladder Diagram(LD) is the must widely utilized and plays an important role in industrial control system. But recently, the study about Sequential Function Chart(SFC) is performed actively. When we program by SFC, generally, we design one routine from start to end. This method is difficult to design, and we often make mistakes. In this paper, we propose the method that we compose each sub-system after we design each sub-system and confirm his feasibility through an actual examples.

• Journal of Institute of Control, Robotics and Systems
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• v.8 no.5
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• pp.401-406
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• 2002

As product lifecycles become shorter, factories are pushed to develop small batches of many different products. The highly flexible control systems has become a necessity. The majority of existing automated industrial systems are controlled by programmable logic controllers(PLCs). In most cases, the control programs for PLCs are developed based on ladder diagrams(LDs). However, it is difficult to debug and maintain those LDs because the synthesis of LD itself mainly depends on the experience of the industrial engineer via trial-and-error methods. Hence, in this paper, we propose a discrete event model conversion algorithm for systematic analysis of LDs. The proposed discrete event model conversion algorithm is illustrated by an example of a conveyor system.

• Proceedings of the KIEE Conference
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• 2006.10c
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• pp.273-275
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• 2006

Ladder Diagram(LD) is the most widely utilized among many sorts of existing programs using for the design of process control system. But it is very difficult to grasp sequential flow of control logic. In this paper, we proposed the method that we can control a lot of blocks. We used PLC in process control system. And, in order to design we used Sequential Function Chart(SFC). In this paper, we proposed the method of block contro. and confirmed feasibility through a simulation.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.19 no.3
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• pp.127-133
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• 2005

Programmable Logic Controller(PLC) is the most widely utilized and plays an important role in industrial control system. The study about a PLC language is performed actively. Ladder Diagram(ID) is the most widely used in PLC. In is not suitable for describing a complex sequential logic and is very difficult to grasp the sequential flow of control logic and has the disadvantage for a maintenance. On the other hand, Sequential Function Chart(SFC) is very easy to grasp the sequential flow of control logic and has the compatability for a maintenance but has the disadvantage for describing a condition and a interlock logic. In this paper, we propose the method that describe the interlock logic using management step, and confirm his feasibility through a actual examples.

• Journal of Institute of Control, Robotics and Systems
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• v.8 no.8
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• pp.706-712
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• 2002

In general, a deadlock in flexible manufacturing systems (FMSs) is caused by a resource limitation and the diversity of routings. However, the deadlock of industrial controllers such as programmable logic controllers (PLCs) can occur from different causes compared with those in general FMSs. The deadlock of PLCs is usually caused by an error signal between PLCs and manufacturing systems. In this paper, we propose a deadlock detection and recovery (DDR) algorithm to resolve the deadlock problem of PLCs at design stage. This paper employs the MAPN (modified automation Petri net), MTPL (modified token passing logic), and ECC (efficient code conversion) algorithm to model manufacturing systems and to convert a Petri net model into a desired LD (ladder diagram). Finally, an example of manufacturing systems is provided to illustrate the proposed DDR algorithm.