A Translation Method of Ladder Diagram for High-Speed Programmable Logic Controller

고속 프로그램형 논리 제어기 구현을 위한 래더 다이어그램 해석 방법

  • 김형석 (서울대학교 전기공학부) ;
  • 장래혁 (서울대학교 컴퓨터공학과) ;
  • 권욱현 (서울대학교 전기공학부)
  • Published : 1999.01.01

Abstract

This paper proposes a translation approach for PLCs (Programmable logic controllers) converting ladder diagrams directly to native codes, and describes detailed steps of the method followed by performance evaluation. A general-purpose DSP (Digital signal processor) based implementation validates the approach as well. A benchmark test shows that the Proposed translation framework fairly speeds up execution in comparison with the existing interpretation approach.

Keywords

References

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