• Steel and Composite Structures
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• v.45 no.4
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• pp.535-546
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• 2022

The memory response of nonlocal systematical formulation size-dependent coupling of viscoelastic deformation and thermal fields for piezoelectric materials with dual-phase lag heat conduction law is constructed. The method of the matrix exponential, which constitutes the basis of the state-space approach of modern control theory, is applied to the non-dimensional equations. The resulting formulation together with the Laplace transform technique is applied to solve a problem of a semi-infinite piezoelectric rod subjected to a continuous heat flux with constant time rates. The inversion of the Laplace transforms is carried out using a numerical approach. Some comparisons of the impacts of nonlocal parameters and time-delay constants for various forms of kernel functions on thermal spreads and thermo-viscoelastic response are illustrated graphically.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.27 no.4
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• pp.775-783
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• 2017

As interest in cloud computing grows, the number of users using cloud computing services is increasing. However, cloud computing technology has been steadily challenged by security concerns. Therefore, various security breaches are springing up to enhance the system security for cloud services users. In particular, research on detection of malicious VM (Virtual Machine) is actively underway through the introspecting virtual machines on the cloud platform. However, memory analysis technology is not used as a monitoring tool in the environments where multiple virtual machines are run on a single server platform due to obstructive monitoring overhead. As a remedy to the challenging issue, we proposes a computationally efficient instance memory introspection scheme to minimize the overhead that occurs in memory dump and monitor it through a partial memory monitoring based on the well-defined kernel memory map library.

• Smart Media Journal
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• v.4 no.4
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• pp.56-63
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• 2015

Modern GPU can execute mass parallel computation by exploiting many GPU core. GPGPU architecture, which is one of approaches exploiting outstanding computational resources on GPU, executes general-purpose applications as well as graphics applications, effectively. In this paper, we investigate the impact of memory-efficiency and performance according to number of CTAs(Cooperative Thread Array) on a SM(Streaming Multiprocessors), since the analysis of relation between number of CTA on a SM and them provides inspiration for researchers who study the GPU to improve the performance. Our simulation results show that almost benchmarks increasing the number of CTAs on a SM improve the performance. On the other hand, some benchmarks cannot provide performance improvement. This is because the number of CTAs generated from same kernel is a little or the number of CTAs executed simultaneously is not enough. To precisely classify the analysis of performance according to number of CTA on a SM, we also analyze the relations between performance and memory stall, dram stall due to the interconnect congestion, pipeline stall at the memory stage. We expect that our analysis results help the study to improve the parallelism and memory-efficiency on GPGPU architecture.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.24 no.5
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• pp.861-870
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• 2014

According to the intelligence of the malicious code to extract the executable file in physical memory is emerging as an import researh issue. In previous physical memory studies on executable file extraction which is targeting running files, they are not extracted as same as original file saved in disc. Therefore, we need a method that can extract files as same as original one saved in disc and also can analyze file-information loaded in physical memory. In this paper, we provide a method that executable file extraction by analyzing information of Windows kernel file object. Also we analyze the characteristic of physical memory loaded file data from the experiment and we demonstrate superiority because the suggested method can effectively extract more of original file data than the existing method.

• The KIPS Transactions:PartA
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• v.14A no.4
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• pp.235-244
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• 2007

Caching and prefetching policies have been used in most of computer systems to compensate speed differences between primary memory and secondary storage devices. In this paper, we design and implement a Flash Cache Core Module(FCCM) on the YAFFS which operates on a file system layer for NAND flash memory. The FCCM is independent of the underlying kernel in order to support its stability and compatibility. Also, we implement the Dirty-Last memory replacement technique considering the characteristics of flash memory, and the waiting queue for pages to be prefetched according to page hit. The FCCM reduced the number of I/Os and the amount of prefetched pages by maximum 55%(20% on average) and maximum 55%(24% on average), respectively, comparing with caching and prefetching policies of Linux.

• KIPS Transactions on Computer and Communication Systems
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• v.11 no.5
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• pp.133-138
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• 2022

Recently, as GPU performance has improved in HPC and artificial intelligence, its use is becoming more common, but GPU programming is still a big obstacle in terms of productivity. In particular, due to the difficulty of managing host memory and GPU memory separately, research is being actively conducted in terms of convenience and performance, and various CPU-GPU memory transfer programming methods are suggested. Meanwhile, recently many SoC (System on a Chip) products such as Apple M1 and NVIDIA Tegra that bundle CPU, GPU, and integrated memory into one large silicon package are emerging. In this study, data between CPU and GPU devices are used in such an integrated memory device and performance-related research is conducted during transmission. It shows different characteristics from the existing environment in which the host memory and GPU memory in the CPU are separated. Here, we want to compare performance by CPU-GPU data transmission method in NVIDIA SoC chips, which are integrated memory devices, and NVIDIA SMX-based V100 GPU devices. For the experimental workload for performance comparison, a two-dimensional matrix transposition example frequently used in HPC applications was used. We analyzed the following performance factors: the difference in GPU kernel performance according to the CPU-GPU memory transfer method for each GPU device, the transfer performance difference between page-locked memory and pageable memory, overall performance comparison, and performance comparison by workload size. Through this experiment, it was confirmed that the NVIDIA Xavier can maximize the benefits of integrated memory in the SoC chip by supporting I/O cache consistency.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.6
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• pp.1301-1306
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• 2011

RTOS in the embedded system is a powerful tool for the design of multi-tasking. However, previous RTOS has large proportion in the MCU with limited memory. So it is difficult to apply RTOS. In this paper, I removed less frequently used features from the traditional RTOS, and designed lightweight RTOS that schedules and manages the resources with minimal code. I used techniques to obtain user memory using sharing stack, and to reduce the overhead at context. Considering ratio of kernel and applications, the RTOS designed in this paper is available on the MCU with more than 4KB of program memory.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.1
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• pp.48-59
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• 2015

In recent years, there are increasing threats of rootkits that undermine the integrity of a system by manipulating OS kernel. To cope with the rootkits, in Vigilare, the snoop-based monitoring which snoops the memory traffics of the host system was proposed. Although the previous work shows its detection capability and negligible performance loss, the problem is that the proposed design is not acceptable in recent commodity mobile application processors (APs) which have become de facto the standard computing platforms of smart devices. To mend this problem and adopt the idea of snoop-based monitoring in commercial products, in this paper, we propose a snoop-based monitor design called S-Mon, which is designed for the AP platforms. In designing S-Mon, we especially consider two design constraints in the APs which were not addressed in Vigilare; the unified memory model and the crossbar switch interconnect. Taking into account those, we derive a more realistic architecture for the snoop-based monitoring and a new hardware module, called the region controller, is also proposed. In our experiments on a simulation framework modeling a productionquality device, it is shown that our S-Mon can detect the rootkit attacks while the runtime overhead is also negligible.

• Journal of Korea Society of Industrial Information Systems
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• v.16 no.1
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• pp.37-48
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• 2011

Sensor networks monitor the environment, collect sensed data, and relay the data back to a collection point. Although sensor nodes have very limited hardware resources, they require an operating system that can provide efficient resource management and various application environments. In addition, the wireless sensor networks require the code update previously deployed to patch bugs in program and to improve performance of kernel service routines and application programs. This paper presents EPRCU (Easy to Perform Remote Code Update), a new operating system for wireless sensor nodes, which has enhanced functionalities to perform remote code update. To achieve an efficient code update, the EPRCU provides dynamic memory allocation and program memory management. It supports the event-driven kernel, which uses priority-based scheduling with the application of aging techniques. Therefore, the proposed operating system is not only easy to perform wireless communication with the remote code update but also suitable for various sensor network applications.

• Journal of KIISE
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• v.42 no.12
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• pp.1486-1494
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• 2015

While Linux-based mobile devices such as smartphones are increasingly used, they often exhibit poor response time. One of the factors that influence the user-perceived interactivity is the high page fault rate of interactive tasks. Pages owned by interactive tasks can be removed from the main memory due to the memory contention between interactive and background tasks. Since this increases the page fault rate of the interactive tasks, their executions tend to suffer from increased delays. This paper proposes a framework-assisted selective page protection mechanism for improving interactivity of Linux-based mobile devices. The framework-assisted selective page protection enables the run-time system to identify interactive tasks at the framework level and to deliver their IDs to the kernel. As a result, the kernel can maintain the pages owned by the identified interactive tasks and avoid the occurrences of page faults. The experimental results demonstrate the selective page protection technique reduces response time up to 11% by reducing the page fault rate by 37%.