• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.42 no.5 s.335
• /
• pp.23-30
• /
• 2005

In the construction of an extension field, there is a connection between the polynomial multiplication method and the degree of polynomial. The existing methods, KO and MSK methods, efficiently reduce the complexity of coefficient-multiplication. However, when we construct the multiplication of an extension field using KO and MSK methods, the polynomials are padded with necessary number of zero coefficients in general. In this paper, we propose basic properties of KO and MSK methods and algorithm that can reduce coefficient-multiplications. The proposed algorithm is more reducible than the original KO and MSK methods. This characteristic makes the employment of this multiplier particularly suitable for applications characterized by specific space constrains, such as those based on smart cards, token hardware, mobile phone or other devices.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.43 no.7 s.349
• /
• pp.115-121
• /
• 2006

The efficiency of the multiplier largely depends on the representation of finite filed elements such as normal basis, polynomial basis, dual basis, and redundant representation, and so on. In particular, the redundant representation is attractive since it can simply implement squaring and modular reduction. In this paper, we propose an efficient bit-parallel multiplier for GF(2m) defined by an irreducible all-one polynomial using a redundant representation. We modify the well-known multiplication method which was proposed by Karatsuba to improve the efficiency of the proposed bit-parallel multiplier. As a result, the proposed multiplier has a lower space complexity compared to the previously known multipliers using all-one polynomials. On the other hand, its time complexity is similar to the previously proposed ones.

• Journal of IKEEE
• /
• v.24 no.4
• /
• pp.961-968
• /
• 2020

This paper describes a design of high performance modular multiplier that is essentially used for elliptic curve cryptography. Our modular multiplier supports modular multiplications for five field sizes over GF(p), including 192, 224, 256, 384 and 521 bits as defined in NIST FIPS 186-2, and it calculates modular multiplication in two steps with integer multiplication and reduction. The Karatsuba-Ofman multiplication algorithm was used for fast integer multiplication, and the Lazy reduction algorithm was adopted for reduction operation. In addition, the Nikhilam division algorithm was used for the division operation included in the Lazy reduction. The division operation is performed only once for a given modulo value, and it was designed to skip division operation when continuous modular multiplications with the same modulo value are calculated. It was estimated that our modular multiplier can perform 6.4 million modular multiplications per second when operating at a clock frequency of 32 MHz. It occupied 456,400 gate equivalents (GEs), and the estimated clock frequency was 67 MHz when synthesized with a 180-nm CMOS cell library.

• Proceedings of the IEEK Conference
• /
• 1998.10a
• /
• pp.771-774
• /
• 1998

In this paper proposes a new bit-parallel structure for a multiplier over GF((Pn)m), with k-nm. Mastrovito Multiplier, Karatsuba-ofman algorithm are applied to the multiplication of polynomials over GF(2n). This operation has a complexity of order O(k log p3) under certain constrains regardig k. A complete set of primitive field polynomials for composite fields is provided which perform modulo reduction with low complexity. As a result, multiplier for fields GF(Pk) with low gate counts and low delays are constructed. The architectures are highly modular and thus well suited for VLSI implementation.

• ETRI Journal
• /
• v.31 no.2
• /
• pp.129-139
• /
• 2009

This paper provides an efficient algorithm for computing the ${\eta}_T$ pairing on supersingular elliptic curves over fields of characteristic two. In the proposed algorithm, we deploy a modified multiplication in $F_{2^{4n}}$ using the Vandermonde matrix. For F, G ${\in}$ $F_{2^{4n}}$ the proposed multiplication method computes ${\beta}{\cdot}F{\cdot}G$ instead of $F{\cdot}G$ with some ${\beta}$ ${\in}$ $F^*_{2n}$ because ${\beta}$ is eliminated by the final exponentiation of the ${\eta}_T$ pairing computation. The proposed multiplication method asymptotically requires only 7 multiplications in $F_{2^n}$ as n ${\rightarrow}$ ${\infty}$, while the cost of the previously fastest Karatsuba method is 9 multiplications in $F_{2^n}$. Consequently, the cost of the ${\eta}_T$ pairing computation is reduced by 14.3%.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.24 no.8
• /
• pp.1044-1051
• /
• 2020

The age of quantum computers is coming soon. In order to prepare for the upcoming future, the National Institute of Standards and Technology has recruited candidates to set standards for post quantum cryptography to establish a future cryptography standard. The submitted ciphers are expected to be safe from quantum algorithm attacks, but it is necessary to verify that the submitted algorithm is safe from quantum attacks using quantum algorithm even when it is actually operated on a quantum computer. Therefore, in this paper, we investigate an efficient quantum gate implementation for binary field multiplication of code based post quantum cryptography to work on quantum computers. We implemented the binary field multiplication for two field polynomials presented by Classic McEliece and three field polynomials presented by ROLLO in generic algorithm and Karatsuba algorithm.