• Journal of IKEEE
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• v.17 no.4
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• pp.544-549
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• 2013

This paper describes a modified binary phase detector (Bang-Bang phase detector - BBPD) for jitter reduction in clock and data recovery (CDR) circuits. The proposed PD reduces ripples in the VCO control voltage resulting in reduced jitter for CDR circuits. A 2.5 Gbps CDR circuit with a proposed BBPD has been designed and verified using Dongbu $0.13{\mu}m$ CMOS technology. Simulation shows the CDR with proposed PD recovers data with peak-to-peak jitter of 10.96ps, rms jitter of 0.86ps, and consumes 16.9mW.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.3
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• pp.232-239
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• 2010

By using the clock timing control at transmitter (TX), the crosstalk-induced jitter (CIJ) is compensated for in the 2-bit parallel data transmission through the coupled microstrip lines on printed circuit board (PCB). Compared to the authors' prior work, the delay block circuit is simplified by combining a delay block with a minimal number of stages and a 3-to-1 multiplexer. The delay block generates three clock signals with different delays corresponding to the channel delay of three different signal modes. The 3-to-1 multiplexer selects one of the three clock signals for TX timing depending on the signal mode. The TX is implemented by using a $0.18\;{\mu}m$ CMOS process. The measurement shows that the TX reduces the RX jitters by about 38 ps at the data rates from 2.6 Gbps to 3.8 Gbps. Compared to the authors' prior work, the amount of RX Jitter reduction increases from 28 ps to 38 ps by using the improved implementation.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.30 no.8
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• pp.126-132
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• 2002

Jitter induced from several payloads on-board satellites degrade the performance of pointing accuracy and attenuate the resolving power of highly-precise camera image such as KOMPSAT II. In this paper, we introduce a micro-vibration measurement technique, analysis of dynamic characteristics, and modeling method for a reaction wheel assembly which is one of the major sources of jitter in satellites and an effective vibration reduction techniques are considered. Based on these techniques, vibration measurement and passive control were performed with an micro-vibration generator which was designed to have similar dynamic performances with an actual reaction wheel assembly above 50Hz.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.4
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• pp.568-576
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• 2017

This paper presents a clock and data recovery circuit with an adaptive loop bandwidth calibration scheme and the idle power saved frequency acquisition. The loop bandwidth calibration adaptively controls injection currents of the main loop with a trimmable bandgap reference circuit and trains the VCO to operate in the linear frequency control range. For stand-by power reduction of the phase detector, a clock gating circuit blocks 8-phase clock signals from the VCO and cuts off the current paths of current mode D-flip flops and latches during the frequency acquisition. 77.96% reduction has been accomplished in idle power consumption of the phase detector. In the jitter experiment, the proposed scheme reduces the jitter tolerance variation from 0.45-UI to 0.2-UI at 1-MHz as compared with the conventional circuit.

• Transactions of the Korean Society for Noise and Vibration Engineering
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• v.22 no.11
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• pp.1042-1048
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• 2012

A 2-axis gimbal system is one of main disturbance sources affecting image jitter response of a satellite. The gimbal system comprises azimuth stage and elevation stage, and these pointing mechanism can be rotated by stepping motors about its azimuth and elevation axes simultaneously. Because of the complex and coupled dynamic motion of the gimbal system, its moment of inertia and structural modes can be changed according to the system configuration, and thus the gimbal system generates complicated and non-linear disturbance characteristics. In order to improve the jitter response of a spacecraft, it is an indispensable process to reduce the micro-vibration disturbance level of the antenna system. In the present research, a 2-axis gimbal system was manufactured and then its micro-vibration test was performed in terms of two types of stepping motors(2-phase and 5-phase). The test results show that the disturbance level of the gimbal system can be reduced by replacing the 2-phase stepping motor with the 5-phase one, and the average disturbance attenuation ratio is 56 % in peak level and 48 % in standard deviation level. The experimental results confirm that it is an efficient jitter reduction method to adopt a high-phase stepping motor.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.4
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• pp.241-246
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• 2007

This paper presents two novel compensation circuits for leakage current and power supply noise (PSN) in phase locked loop (PLL) using a nanometer CMOS technology. The leakage compensation circuit reduces the leakage current of the charge pump circuit and the PSN compensation circuit decreases the effect of power supply variation on the output frequency of VCO. The PLL design is based on a 32nm predictive CMOS technology and uses a 0.9 V power supply voltage. The simulation results show that the proposed PLL achieves 88% jitter reduction at 440 MHz output frequency compared to the PLL without leakage compensator and its output frequency drift is little to 20% power supply voltage variations. The PLL has an output frequency range of 40 $M{\sim}725$ MHz with a multiplication range of 1-1023, and the RMS and peak-to-peak jitter are 5psec and 42.7 psec, respectively.

• Proceedings of the KIEE Conference
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• 2004.11a
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• pp.123-125
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• 2004

In order to achieve high efficiency and low cost, new high-speed addressing method is suggested. This can be achieved by reducing the address discharge delay time through the priming effect. This paper suggests a new ADR (Address During Reset) driving method which provides priming particles by using a separated driving method without adding auxiliary electrode or auxiliary discharge. The experimental results show an approximately loons reduction in the formative delay time of address discharge and a reduction in jitter of over 200ns. Also, due to enough time being available for reset, there was a reduction in light emitted during reset of about 29% which improved the dark contrast ratio considerably.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.54 no.6
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• pp.269-273
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• 2005

In order to achieve high efficiency and low cost, new high-speed addressing method is suggested. This can be implemented by reducing the address discharge time lag through the priming effect. This paper suggests a new ADR(Address During Reset) driving method which provides priming particles by a separated driving method without adding auxiliary electrode or auxiliary discharge. The experimental results show an approximately 100ns reduction in the formative delay time of address discharge and a reduction in jitter of over 200ns. Also, due to enough time being available for reset, there was a reduction of about 29$\%$ in linht emitted during the reset period considerably.

• Journal of IKEEE
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• v.13 no.4
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• pp.96-102
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• 2009

We investigate the characteristics of RJ (random jitter) in an analog fiber-optic link employing a MZM (Mach-Zehnder modulator) and an EDFA (Erbium-doped fiber amplifier). RJ has been measured using two methods, one of which derived from the noise spectrum of a RF spectrum analyzer and the other from the histogram data of a sampling oscilloscope. If the optical power and/or the RF power input to the MZM increase, RJ decreases due to the output signal power increase. For the optical link without EDFA, the minimum RJ is about 1 ps at an RF power of 10 dBm and an optical power of 8 dBm measured using the noise spectrum method. For the optical link with an EDFA, RJ decreases toward a jitter floor as the EDFA gain increases. If the gain increases further, it has been observed that RJ increases from the minimum. If the EDFA gain is fixed, RJ is smaller for the case of larger optical input power. As the EDFA gain increases, RJ reduction rate becomes greater for the case of lower optical input power.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 1999.11b
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• pp.225-228
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• 1999

Network의 QoS를 결정하는 인자에는 손실과 지연, jitter 등이 있다. 그 중에서 손실의 양을 최소화하기 위하여 패킷의 크기를 될 수 있는 한 작게 보냄으로서 라우터에서 생기는 손실을 최소화하는 방법이 있다. 본 연구에서는 비디오 데이터의 전송에 있어서 패킷의 크기를 현재 망의 상황에 고려하여 여러 개의 소켓으로 나누어 보냄으로서 손실의 양을 최소화한다.