• Journal of the Institute of Electronics Engineers of Korea TC
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• v.40 no.7
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• pp.293-299
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• 2003

In this paper, we have proposed a high conversion and isolation characteristic V-band quadruple sub-harmonic mixer monolithic circuit which is designed and fabricated for the millimeter wave down converter applications. While most of the sub-harmonic mixers use a half of fundamental frequency, we adopt a quarter of the fundamental frequency. The proposed circuit is based on a sub-harmonic mixer with APDP(anti-parallel diode pair) and the 0.1 ${\mu}{\textrm}{m}$ PHEMT's (pseudomorphic high electron mobility transistors). Lumped elements at IF port provide better selectivity of IF frequency and increase isolation. Maximum conversion gain of 0.8 ㏈ at a LO frequency of 14.5㎓ and at a RF frequency of 60.4 ㎓ is measured. Both LO-to-RF and LO-to-IF isolations are higher than 50 ㏈. The conversion gain and isolation characteristic are the best performances among the reported quadruple sub-harmonic mixer operating in the V-band millimeter wave frequency thus far.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.5
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• pp.70-75
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• 2007

A dual-frequency dual-polarization (DFDP) antenna with high isolation between two ports by embedding $2{\times}1$ mushroom-like electromagnetic bandgap (EBG) cells is proposed. The equivalent circuit of a suspended microstrip line over $2{\times}1$ EBG cells is introduced. The numerical analysis from the equivalent circuit and measured results show that the microstrip line with embedded EBG cells has a distinctive and sharp rejection band and provides near 0 dB insertion loss outside the rejection band. By embedding the EBG cells under feedlines of a conventional DFDP antenna, the isolation between two ports of the antenna is enhanced more than 20 dB, as compared to that of a conventional DFDP antenna. The proposed DFDP antenna is fabricated and measured. The simulated and measured results show a good agreement. The measured polarization purity and gain of the antenna are 25 dB and 5.77 dBi at lower band, and 35 dB and 7.13 dBi at higher band, respectively.

• ETRI Journal
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• v.27 no.5
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• pp.569-578
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• 2005

The purpose of this paper is to describe the implementation of monolithically matching circuits, interface circuits, and RF core circuits to the same substrate. We designed and fabricated on-chip 1 to 6 GHz up-conversion and 1 to 8 GHz down-conversion mixers using a 0.8 mm SiGe hetero-junction bipolar transistor (HBT) process technology. To fabricate a SiGe HBT, we used a reduced pressure chemical vapor deposition (RPCVD) system to grow a base epitaxial layer, and we adopted local oxidation of silicon (LOCOS) isolation to separate the device terminals. An up-conversion mixer was implemented on-chip using an intermediate frequency (IF) matching circuit, local oscillator (LO)/radio frequency (RF) wideband matching circuits, LO/IF input balun circuits, and an RF output balun circuit. The measured results of the fabricated up-conversion mixer show a positive power conversion gain from 1 to 6 GHz and a bandwidth of about 4.5 GHz. Also, the down-conversion mixer was implemented on-chip using LO/RF wideband matching circuits, LO/RF input balun circuits, and an IF output balun circuit. The measured results of the fabricated down-conversion mixer show a positive power conversion gain from 1 to 8 GHz and a bandwidth of about 4.5 GHz.

• Proceedings of the KIPE Conference
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• 2001.10a
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• pp.683-686
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• 2001

This paper presents a novel prototype of the utility­interactive voltage source type sinewave pulse modulated power inverter using a high-frequency flyback transformer link. The proposed power conditioner circuit for the solar photovoltaic generation and small scale fuel cell has an isolation function due to the safety of the power processing system, which is more cost effective and acceptable for the small-scale distributed renewal energy conditioning and processing systems. The discontinuous current mode(DCM) of this power processing conversion circuit is applied to implement a simple circuit topology and pulse modulated control scheme. Its operation principle is described on the basis of simulation evaluations and theoretical considerations. The simulation results obtained herein prove that the proposed inverter outputs with sinusoidal waveforms and unity power factor currents are synchronized to the main voltage in utility power source grid. In this paper, the soft switching topology of high­frequency linked sinewave pulse modulation inverter is proposed and discussed.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.5
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• pp.595-604
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• 2016

Utilizing a standard 130-nm CMOS process, a RF frontend is designed at 24 GHz for automotive collision avoidance radar application. Single IF direct conversion receiver (DCR) architecture is adopted to achieve high integration level and to alleviate the DCR problem. The proposed frontend is composed of a two-stage LNA and downconversion mixers. To save power consumption, and to enhance gain and linearity, stacked NMOS-PMOS $g_m$-boosting technique is employed in the design of LNA as the first stage. The switch transistors in the mixing stage are biased in subthreshold region to achieve low power consumption. The single balanced mixer is designed in PMOS transistors and is also realized based on the well-known folded architecture to increase voltage headroom. This frontend circuit features enhancement in gain, linearity, and power dissipation. The proposed circuit showed a maximum conversion gain of 19.6 dB and noise figure of 3 dB at the operation frequency. It also showed input and output return losses of less than -10 dB within bandwidth. Furthermore, the port-to-port isolation illustrated excellent characteristic between two ports. This frontend showed the third-order input intercept point (IIP3) of 3 dBm for the whole circuit with power dissipation of 6.5 mW from a 1.5 V supply.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.571-574
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• 2008

In this paper, we propose $256{\times}256$ pixel array fingerprint sensor with an advanced circuits for detecting. The pixel level simple detection circuit converts from a small and variable sensing current to binary voltage out effectively. We minimizes an electrostatic discharge(ESD) influence by applying an effective isolation structure. The sensor circuit blocks were designed and simulated in standard CMOS $0.35{\mu}m$ process. Full custom layout is performed in the unit sensor pixel and auto placement and routing is performed in the full chip.

• Proceedings of the IEEK Conference
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• summer
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• pp.82-85
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• 2004

This paper proposes an advanced circuit for the capacitive type fingerprint sensor signal processing and an effective isolation structure for minimizing an electrostatic discharge(ESD) influence and for removing a signal coupling noise of each sensor pixel. The proposed detection circuit increases the voltage difference between a ridge and valley about $80\%$ more than old circuit. The test chip is composed of $160\;\times\;192$ array sensing cells $(9,913\times11,666\;um^2).$ The sensor plate area is $58\;\times\;58\;um^2$ and the pitch is 60um. The image resolution is 423 dpi. The chip was fabricated on a 0.35um standard CMOS process. It successfully captured a high-quality fingerprint image and performed the registration and identification processing. The sensing and authentication time is 1 sec(.) with the average power consumption of 10 mW at 3.0V. The reveal ESD tolerance is obtained at the value of 4.5 kV.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.3
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• pp.531-536
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• 2009

In this paper, we propose $256{\times}256$ pixel array fingerprint sensor with an advanced circuits for detecting. The pixel level simple detection circuit converts from a small and variable sensing current to binary voltage out effectively. We minimizes an electrostatic discharge(ESD) influence by applying an effective isolation structure around the unit pixel. The sensor circuit blocks were designed and simulated in standard CMOS $0.35{\mu}m$ process. Full custom layout is performed in the unit sensor pixel and auto placement and routing is performed in the full chip.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.8 no.5
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• pp.1076-1081
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• 2007

In this paper, we propose a new switch structure for time division duplex(TDD) system. The existing TDD structure utilizes a circulator fur isolation characteristic between ports. However, the circulator produces intermodulation distortion signals which are undesired signal because of its nonlinear properties. The proposed circuit is composed of a modified branch-line hybrid coupler which controls the signal flow while the isolated port is open-/short- terminated. In order to prove the validity of the presented structure, the switch circuit is fabricated and measured at 2.3GHz, the center frequency of Wibro service system.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.4 no.4
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• pp.817-824
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• 2000

This paper presents circuit DQ modeling and analysis of operating characteristics of hybrid cascade multilevel PWM rectifier, especially five-level, without isolation transformers. The circuit DQ transformation changes the original three-phase time varying circuit to stationary equivalent one by employing the synchronously rotating transformation matrix. As a result of circuit DQ modeling, the operating characteristics and some useful design relationships for the system are obtained with ease. That is, the analytic equations for DC voltages and active/reactive power supplied by source with respect to control variables are Presented. Moreover, the DC voltages for the multilevel output generation may be directly built up from AC utility source and the important control equation ensuring 5-level output voltage is obtained. Finally, to confirm the validity of the analysis, MATLAB simulations are carried out and the simulation results show good agreements between analytic predictions and the simulated waveforms.