• Journal of the Korean Mathematical Society
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• v.55 no.3
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• pp.705-717
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• 2018

We construct some infinite series of free and nearly free curves using pencils of conics with a base locus of cardinality at most two. These curves have an interesting topology, e.g. a high degree Alexander polynomial that can be explicitly determined, a Milnor fiber homotopy equivalent to a bouquet of circles, or an irreducible translated component in the characteristic variety of their complement. Monodromy eigenspaces in the first cohomology group of the corresponding Milnor fibers are also described in terms of explicit differential forms.

• Journal of information and communication convergence engineering
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• v.8 no.3
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• pp.317-322
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• 2010

This paper presents an algorithm generating inverse element over finite fields GF($3^m$), and constructing method of inverse element generator based on inverse element generating algorithm. An inverse computing method of an element over GF($3^m$) which corresponds to a polynomial over GF($3^m$) with order less than equal to m-1. Here, the computation is based on multiplication, square and cube method derived from the mathematics properties over finite fields.

• Proceedings of the KIEE Conference
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• 2002.11c
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• pp.268-273
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• 2002

In this paper, a new parallel multiplier circuit over $GF(2^m)$ has been proposed. The new multiplier is composed of polynomial multiplicative operation part and modular arithmetic operation part, irreducible polynomial operation part. And each operation has modular circuit block. For design the new proposed circuit, it develop generalized equations using frame each operation idea and show a example for $GF(2^m)$.

• Proceedings of the Korean Information Science Society Conference
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• 2003.04a
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• pp.521-523
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• 2003

본 논문에서는 프로그램 가능한 셀룰라 오토마타(Programmable Cellular Automata, PCA)를 이용한 곱셈기를 제안한다. 본 논문에서 제안한 구조는 연산 후 늘어나는 원소의 수를 제한하기 위하여 이용되는 기약다항식(irreducible polynomial)으로서 All One Polynomial(AOP)을 사용하며, 주기적 경계 셀룰라 오토마타(Periodic Boundary Cellular Automata, PBCA)의 구조적인 특성을 사용함으로써 정규성을 높이고 하드웨어 복잡도와 시간 복잡도를 줄일 수 있는 장점을 가지고 있다. 제안된 곱셈기는 시간적. 공간적인 면에서 아주 간단히 구성되어 지수연산을 위한 하드웨어 설계나 오류 수정 코드(error correcting code)의 연산에 효율적으로 이용될 수 있을 것이다.

• Journal of Korea Society of Industrial Information Systems
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• v.8 no.3
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• pp.85-90
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• 2003

This paper proposes a modular multiplier based on LFSR (Linear Feedback Shift Register) architecture with efficient area complexity over GF(2/sup m/). At first, we examine the modular exponentiation algorithm and propose it's architecture, which is basic module for public-key cryptosystems. Furthermore, this paper proposes on efficient modular multiplier as a basic architecture for the modular exponentiation. The multiplier uses AOP (All One Polynomial) as an irreducible polynomial, which has the properties of all coefficients with '1 ' and has a more efficient hardware complexity compared to existing architectures.

• Communications of the Korean Mathematical Society
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• v.34 no.2
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• pp.401-414
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• 2019

Let ${\mathcal{F}}$ denote an algebraically closed field with characteristic not two. Fix an integer $d{\geq}3$, let $Mat_{d+1}({\mathcal{F}})$ denote the ${\mathcal{F}}$-algebra of $(d+1){\times}(d+1)$ matrices with entries in ${\mathcal{F}}$. An ordered pair of matrices A, $A^*$ in $Mat_{d+1}({\mathcal{F}})$ is said to be LB-TD form whenever A is lower bidiagonal with subdiagonal entries all 1 and $A^*$ is irreducible tridiagonal. Let A, $A^*$ be a Leonard pair in $Mat_{d+1}({\mathcal{F}})$ with fundamental parameter ${\beta}=2$, with this assumption there are four families of Leonard pairs, Racah, Hahn, dual Hahn, Krawtchouk type. In this paper we show from these four families only Racah and Krawtchouk have LB-TD form.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.7 s.349
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• pp.115-121
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• 2006

The efficiency of the multiplier largely depends on the representation of finite filed elements such as normal basis, polynomial basis, dual basis, and redundant representation, and so on. In particular, the redundant representation is attractive since it can simply implement squaring and modular reduction. In this paper, we propose an efficient bit-parallel multiplier for GF(2m) defined by an irreducible all-one polynomial using a redundant representation. We modify the well-known multiplication method which was proposed by Karatsuba to improve the efficiency of the proposed bit-parallel multiplier. As a result, the proposed multiplier has a lower space complexity compared to the previously known multipliers using all-one polynomials. On the other hand, its time complexity is similar to the previously proposed ones.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.7
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• pp.1209-1217
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• 2008

In this paper, we present a new bit-parallel multiplier for performing the bit-parallel multiplication of two polynomials in the finite fields $GF(2^m)$. Prior to construct the multiplier circuits, we consist of the vector code generator(VCG) to generate the result of bit-parallel multiplication with one coefficient of a multiplicative polynomial after performing the parallel multiplication of a multiplicand polynomial with a irreducible polynomial. The basic cells of VCG have two AND gates and two XOR gates. Using these VCG, we can obtain the multiplication results performing the bit-parallel multiplication of two polynomials. Extending this process, we show the design of the generalized circuits for degree m and a simple example of constructing the multiplier circuit over finite fields $GF(2^4)$. Also, the presented multiplier is simulated by PSpice. The multiplier presented in this paper use the VCGs with the basic cells repeatedly, and is easy to extend the multiplication of two polynomials in the finite fields with very large degree m, and is suitable to VLSI.

• Bulletin of the Korean Mathematical Society
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• v.46 no.2
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• pp.229-234
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• 2009

We find congruences for the t-expansion coefficients of a Drinfeld modular form for ${\Gamma}^+_0$(Q), where Q is a monic irreducible polynomial. As an application we obtain new congruence relations for the t-expansion coefficients of Drinfeld modular forms for ${GL_2}(\mathbb{F}_q[T])$.

• Journal of Korea Society of Industrial Information Systems
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• v.10 no.3
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• pp.57-63
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• 2005

Kim and Fenn et al. proposed two modular AB multipliers based on LFSR(Linear Feedback Shift Register) architecture. These multipliers use AOP, which has all coefficients with '1', as an irreducible polynomial. Thereby, they have good hardware complexity compared to the previous architectures. This paper proposes a modular $AB^2$ multiplier based on LFSR architecture and a modular exponentiation architecture to improve the hardware complexity of the Kim's. Our multiplier also use the AOP as an irreducible polynomial as the Kim architecture. Simulation result shows that our multiplier reduces the hardware complexity about $50\%$ in the perspective of XOR and AND gates compared to the Kim's. The architecture could be used as a basic block to implement public-key cryptosystems.