• ETRI Journal
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• v.25 no.5
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• pp.297-304
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• 2003

A multimedia SoC often requires a large internal buffer, because it must store the whole search window to reduce the huge I/O bandwidth of motion estimation. However, the silicon area of the internal buffer increases tremendously as the search range becomes larger. This paper proposes a new method that greatly reduces the internal buffer size of a multimedia SoC while the computational cost, I/O bandwidth, and image quality do not change. In the proposed method, only the overlapped parts of search windows for consecutive macroblocks are stored in the internal buffer. The proposed method reduces the internal buffer. The proposed method reduces the internal buffer size to 1/5.0 and 1/8.8 when the search range is ${\pm}64{\times}{\pm}$64 and ${\pm}128{\times}{\pm}$128, respectively.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39B no.2
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• pp.86-94
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• 2014

Optical packet switching (OPS) is being considered as one of the switching technologies for a future optical internet. For contention resolution in an optical packet switching (OPS) system, the wavelength dimension is generally used in combination with a fiber delay line (FDL) buffer. In this article, we propose a method to reduce the number of tunable wavelength converters (TWCs) by sharing TWCs for a cost-effective design of an asynchronous OPS system with a shared or an output FDL buffer. Asynchronous and variable-length packets are considered in the OPS system design. To investigate the number of TWCs needed for the OPS system, an algorithm is proposed, which searches for an available TWC and an unused internal wavelength, as well as an outgoing channel. This algorithm is applied to an OPS system with a shared or an output FDL buffer. Also, the number of internal wavelengths (i.e., the conversion range of the TWC) needed for an asynchronous OPS system is presented for cost reduction of the OPS system.

• Journal of IKEEE
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• v.5 no.1 s.8
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• pp.52-58
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• 2001

This paper describes a TTL-to-CMOS input buffer of an SRAM which dissipates a small operating power dissipation. The input buffer utilizes a transistor structure with latch circuit controlled by a internal activation clock pulse. During the low state of that pulse, input buffer is disabled to eliminate dc current. Otherwise, the input buffer operates normally. Simulation results showed that the power-delay product of the purposed input buffer is reduced by 33.7% per one input.

• Journal of Internet Computing and Services
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• v.10 no.2
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• pp.171-177
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• 2009

Optical packet switching(OPS) is a strong candidate for the next-generation internet, since it has a fine switching granularity at the packet level for providing flexible bandwidth, and provides seamless integration between WDM layer and IP layer. Optical packet switching have been studied in two categories: OPS in synchronous and OPS in asynchronous networks. In this article we are focused on contention resolution of OPS in asynchronous networks. The hybrid buffer have been addressed, to reduce packet loss further as one of the alternative buffer structures for contention resolution of asynchronous and variable length packets, which consists of the FDL buffer and the electronic buffer. The OPS design issue for the limited number of TWCs and internal wavelengths is important in the aspect of switch cost and resource efficiency. Therefore, an hybrid buffer structured optical packet switch and its scheduling algorithm is presented for considering the limited number of TWCs and internal wavelengths, for contention resolution of asynchronous and variable length packets. The proposed algorithm could lead to the packet loss improvement compared to the legacy LAUC-VF algorithm with only the FDL buffer.

• Electrical & Electronic Materials
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• v.8 no.2
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• pp.204-210
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• 1995

The characteristics of the internal circuits and the load capacitance should be included to optimize the size of BiCMOS buffer. In order to get the optimum size and delay time of the BiCMOS buffer, new size plane is suggested. By using the size plane, the optimum characteristics of CMOS buffer according to the number of stages can be obtained. From this method, delaytime, .tau.$_{D}$, is obtained 2.39 nsec with $V_{\var}$=5V, $C_{L}$=5pF, W=30.mu.m and $A_{e}$=135.mu. $m^{2}$.>..>...>.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.2B
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• pp.1-10
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• 2005

TCP/IP protocols have been implemented in software program running on CPU in end systems. As the increased demand of fast protocol processing, it is required to implement the protocols in hardware, and Host Interface is responsible for communication between external CPU and the hardware blocks of TCP/IP implementation. The Host Interface follows AMBA AHB specification for the communication with external world. For control flow, the Host Interface behaves as a slave of AMBA AHB. Using internal Command/status Registers, the Host Interface receives commands from CPU and transfers hardware status and header information to CPU. On the other hand, the Host Interface behaves as a master for data flow. Data flow has two directions, Receive Flow and Transmit Flow. In Receive Flow, using internal RxFIFO, the Host Interface reads data from UDP FIFO or TCP buffer and transfers data to external RAM for CPU to read. For Transmit Flow, the Host Interface reads data from external RAM and transfers data to UDP buffer or TCP buffer through internal TxFIFO. TCP/IP hardware blocks generate packets using the data and transmit. Buffer Descriptor is one of the Command/Status Registers, and the information stored in Buffer Descriptor is used for external RAM access. Several testcases are designed to verify TCP/IP functions. The Host Interface is synthesized using the 0.18 micron technology, and it results in 173 K gates including the Command/status Registers and internal FIFOs.

• Journal of Internet Computing and Services
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• v.7 no.6
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• pp.113-121
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• 2006

To reduce switch cost, the optimum numbers of tunable wavelength converters (TWCs) and internal wavelengths required for contention resolution of asynchronous and variable length packets like internet traffics, is presented in the optical packet switch (OPS) with the shared fiber delay line (FDL) buffer. To optimize TWCs and internal wavelength related to on OPS design cost, we proposed a scheduling algorithm for the limited TWCs and internal wavelengths. For three TWC alternatives (not shared, partially shared, and fully shared cases), the optimum numbers of TWCs and internal wavelengths to guarantee minimum pocket loss are evaluated to prevent resource waste. Under o given load, TWCs and internal wavelengths could be significantly reduced, guaranteeing the same pocket loss probability as the performance of on OPS with full TWCs and internal wavelengths.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.9
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• pp.38-45
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• 2007

With the emergence of new applications, packet classification is essential for supporting advanced internet applications, such as network security and QoS provisioning. As the packet classification on multiple-fields is a difficult and time consuming problem, internet routers need to classify incoming packet quickly into flows. In this paper, we present multi-phase packet classification architecture using an internal buffer for fast packet processing. Using internal buffer between address pair searching phase and remained fields searching phases, we can hide latency from the characteristic that search times of source and destination header fields are different. Moreover we guarantee the improvement by using single entry caching. The proposed architecture is easy to apply to different needs owing to its simplicity and generality.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.2 no.2
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• pp.181-186
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• 1998

This paper presents multiplexing structures to provide various subscriber interfaces in an ATM switching system with a high speed internal link, and analyzes the schemes in terms of a mean cell delay and a buffer sin. And we proposed a buffer management strategy to minimize a cell loss and accommodate new ATM transfer capabilities.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• 2000.11a
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• pp.121-129
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• 2000

In this paper, we discuss how to operate a buffer yard in an automated container terminal, which will be used for resolving the difficulties to which the interaction between external manned trucks and internal unmanned equipment led. The determination of fleet size of material handling equipment is an important issue in designing of buffer yard in automated container terminals. This research also addresses the issue of determining buffer capacities through simulation. By using response surface methodology (RSM) for efficient experimentation, the optimal combination of design parameters under applicable operational strategies is obtained.