• Title/Summary/Keyword: Interface circuit

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A Study on The Design of High Speed-Low Voltage LVDS Driver Circuit with Novel ESD Protection Device (새로운 구조의 ESD 보호소자를 내장한 고속-저 전압 LVDS 드라이버 설계에 관한 연구)

  • Kim, Kui-Dong;Kwon, Jong-Ki;Lee, KJae-Hyun;Koo, Yong-Seo
    • Journal of IKEEE
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    • v.10 no.2 s.19
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    • pp.141-148
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    • 2006
  • In this study, the design of advanced LVDS(Low Voltage Differential Signaling) I/O interface circuit with new structural low triggering ESD (Electro-Static Discharge) protection circuit was investigated. Due to the differential transmission technique and low signal swing range, maximum transmission data ratio of designed LVDS transmitter was simulated to 5Gbps. And Zener Triggered SCR devices to protect the ESD Phenomenon were designed. This structure reduces the trigger voltage by making the zener junction between the lateral PNP and base of lateral NPN in SCR structure. The triggering voltage was simulated to 5.8V. Finally, The high speed I/O interface circuit with the low triggered ESD protection device in one-chip was designed.

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Web-based Measurement of ECU Signals on Vehicle using Embedded Linux

  • Choi, Kwang-Hun;Lee, Lee;Lee, Young-Choon;Kwon, Tae-Kyu;Lee, Seong-Cheol
    • 제어로봇시스템학회:학술대회논문집
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    • 2004.08a
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    • pp.138-142
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    • 2004
  • In this paper, we present a new method for monitoring of ECU's sensor signals of vehicle. In order to measure the ECU's sensor signals, the interfaced circuit is designed to communicate ECU and the Embedded Linux is used to monitor communication result through Web the Embedded Linux system and this system is said "ECU Interface Part". In ECU Interface Part the interface circuit is designed to match voltage level between ECU and SA-1110 micro controller and interface circuit to communicate ECU according to the ISO, SAE communication protocol standard. Because Embedded Linux does not allow to access hardware directly in application level, anyone who wants to modify any low level hardware must develop device driver. To monitor ECU's sensor signals the most important thing is to match serial level between ECU and ECU Interface Part. It means to communicate correctly between two hardware we need to match voltage and signal level, and need to match baudrate. The voltage of SA-1110 is 0 ${\sim}$ +3.3V and ECU is 0 ${\sim}$ +12V and, ECU's communication Line K does multiple operation so, the interface circuit is used to match voltage and signal level. In Addition to ECU's baudrate is 10400bps, it's not standard baudrate in computer environment. So, we need to develop a device driver to control the interface circuit, and change baudrate. To monitor ECU's sensor signals through web there's a network socket program is working in Embedded Linux. It works as server program and manages user's connections and commands. Anyone who wants to monitor ECU's sensor signals he just only connect to Embedded Linux system with web browser then, Embedded Linux webserver will return the ActiveX webbased measurement software. It works in web browser and inits ECU, as a result it returns sensor signals through web. All the programs are developed with GCC(GNU C Compiler) and, webbased measurement software is developed with Borland C++ Builder.

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Design of myoelectrical sensor for myoelectric hand prosthesis (전동의수용 근전위 센서 설계)

  • Choi, Gi-Won;Choe, Gyu-Ha
    • Proceedings of the KIPE Conference
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    • 2007.07a
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    • pp.247-249
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    • 2007
  • This paper proposes a dry-type surface myoelectric sensor for the myoelectric hand prosthesis. The designed surface myoelectric sensor is composed of skin interface and processing circuits. The skin interface has one reference and two input electrodes, and the reference electrode is located in the center of two input electrodes. Considering the conduction velocity and the median frequency of the myoelectric signal, the inter-electrode distance (IED) between two input electrodes as 18mm, 20mm, and 22mm is selected. The signal processing circuit consists of a differential amplifier with a band pass filter, a band rejection filter for rejecting 60㎐ power-line noise, amplifier, and a level circuit. Using SUS440, six prototype skin interface with different reference electrode shape and IED is fabricated, and their output characteristics are evaluated by output signal obtained from the forearm of a healthy subject. The experimental results show that the skin interface with parallel bar shape and the 18mm IED has a good output characteristics. The fabricated dry-type surface myoelectric sensor is evaluated for the upper-limb amputee.

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An Application of Heuristic Algorithms for the Large Scale Traveling Salesman Problem in Printed Circuit Board Production (회로기판 생산에서의 대형 외판원문제를 위한 경험적 해법의 응용)

  • 백시현;김내헌
    • Journal of Korean Society of Industrial and Systems Engineering
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    • v.20 no.41
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    • pp.177-188
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    • 1997
  • This study describes the important information for establishing Human Computer Interface System for solving the large scale Traveling Saleman Problem in Printed Circuit Board production. Appropriate types and sizes of partitioning of large scale problems are discussed. Optimal tours for the special patterns appeared in PCB's are given. The comparision of optimal solutions of non-Euclidean problems and Euclidean problems shows the possibilities of using human interface in solving the Chebyshev TSP. Algorithm for the large scale problem using described information and coputational result of the practical problem are given.

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A Switched-Capacitor Interface Based on Dual-Slope Integration (이중-적분을 이용한 용량형 센서용 스위치드-캐패시터 인터페이스)

  • 정원섭;차형우;류승용
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.26 no.11
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    • pp.1666-1671
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    • 1989
  • A novel switched-capacitor circuit for interfacing capacitive microtransducers with a digital system is developed based on the dual-slope integration. It consists of a differential integrator and a comparator. Driven by the teo phase clock, the circuit first senses the capacitance difference between the transducer and the reference capacitor in the form of charge, and accumulates it into the feedback capabitor of the integrator for a fixed period of time. The resulant accumulated charge is next extracted by the known reference charge until the integrator output voltage refurns to zero. The length of time required for the integrator output to return to zero, as measured by the number of clock cycle gated into a counter is proportional to the capacitance difference, averaged over the integration period. The whole operation is insensitive to the reference voltage and the capacitor values involved in the circuit, Thus the proposed circuit permits an accurate differental capacitance measurement. An error analysis has showh that the resolution as high as 8 bits can be expected by realizing the circuit in a monolithic MOS IC form. Besides the accuracy, it features the small device count integrable onto a small chip area. The circuit is thus particularly suitadble for the on-chip interface.

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Design of an Interface System IC for Automobile ABS/TCS (자동차용 ABS/TCS 인터페이스 시스템 IC의 설계)

  • Lee, Sung-Pil;Kim, Chan
    • Journal of the Institute of Convergence Signal Processing
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    • v.7 no.4
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    • pp.195-200
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    • 2006
  • The conventional discrete circuit for ABS/TCS system was examined and the problems of the system were analyzed by computer simulation. In order to improve the performance of ABS/TCS system, interface IC which has error compensation, comparator and under voltage lock-out circuit was designed and their electrical characteristics were investigated. The voltage regulator was included to compensate the temperature variation in the temperature range from $-20^{\circ}C$ to $120^{\circ}C$ for automobile environment. ABS and brake signal were separated using the duty factor of same frequency or different frequencies. UVLO(Under Voltage Lock-Out) circuit and constant current circuit were applied for the elimination of noise, and protection circuit was applied to cut the excess current off. Layout for IC fabrication was designed to enhance the electrical performance of ABS/TCS system. Layout was consisted of 11 masks, arrayed effectively 8 pads to reduce the current loss. We can see that the result of layout simulation was better than the result of bread board.

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A Study on Extension of One-bit of the Parallel Interface type Digital-to-Analog Conversion Circuit (병렬 인터페이스형 디지털/아날로그 변환회로의 1개 비트 확장에 관한 연구)

  • Kwon, Sung-Yeol;Lee, Hyun-Chang
    • Journal of Convergence for Information Technology
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    • v.11 no.8
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    • pp.1-7
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    • 2021
  • In this paper, a method of extending 1 bit by adding an external device to a parallel interface type Digital-to-Analog conversion(D/A C) circuit is presented. To do this, the principle of the D/A C circuit was examined, and the problems that occur when extending one bit by adding individual devices were analyzed, and a bit extension method of the D/A devices using an OP-Amp. circuit was presented. As the proposed method uses the high-precision characteristics of the OP-Amp., even if an error occurs in the device, only the overall size of the output waveform is affected, and the voltage reversal phenomenon that occurs between each bit does not occur. In order to confirm the effect of the proposed method, an experimental circuit was constructed and the absolute voltage of the output and the relative error were measured. As a result, a voltage error of 0.0756% appeared, confirming that the 0.195% requirement for one bit expansion by adding individual devices was sufficiently satisfied.

Design of an Integrated Interface Circuit and Device Driver Generation System (인터페이스 회로와 디바이스 드라이버 통합 자동생성 시스템 설계)

  • Hwang, Sun-Young;Kim, Hyoun-Chul;Lee, Ser-Hoon
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.32 no.6B
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    • pp.325-333
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    • 2007
  • An OS requires the device driver to control hardware IPs at application level. Development of a device driver requires specific acknowledge for target hardware and OS. In this paper, we present a system which generates a device driver together with an interface circuit. In the proposed system, an efficient device driver is generated by selecting a basic device driver skeleton, a function module code, and a header file table from the pre-constructed library and an interface circuit is constructed such that the generated device driver operates correctly. The proposed system is evaluated by generating a TFT-LCD device driver on the ARM922T core with 3.5 inch Samsung TFT-LCD in ARM-Linux environment. Experiment result shows that the writing time on the LCD is decreased by 1.12% and the compiled code size is increased by 0.17% compared to the manually generated one. The automatically generated device driver has no performance degradation in the latency of hardware control at the application program level. The system development time can be reduced using the proposed device driver generation system.

Design of ATM Mux/demux Circuit in the BSC for IMT-2000 Network (IMT-2000 망의 제어국에서 ATM 다중/역다중화 회로 설계)

  • 이인환;이남준오돈성
    • Proceedings of the IEEK Conference
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    • 1998.10a
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    • pp.51-54
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    • 1998
  • In this paper, we describe the design of the ATM Mux/Demux circuit between BSC and MSC for IMT-2000 Network. This ATM Mux/Demux circuit culd support 155Mbps optic interface with MSC. Using the CAM and DPRAM, this circuit performs ATM cell Mux/Demux functions in the BSC. MPC 860SAR processor was used for the signaling with MSC in this design.

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Implementation of FPGA Verification System with Slave FIFO Interface and FX3 USB 3 Bridge Chip (FX3 USB 3 브릿지 칩과 slave FIFO 인터페이스를 사용하는 FPGA 검증 시스템 구현)

  • Choi, Byeong-Yoon
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.25 no.2
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    • pp.259-266
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    • 2021
  • USB bus not only works with convenience but also transmits data fast and becomes a standard peripheral interface between FPGA development board and personal computer. In this paper FPGA verification system with slave FIFO interface for Cypress FX3 USB 3 bridge chip was implemented. The designed slave FIFO interface consists of host interface module based on FIFO structure, master bus controller and command decoder and supports streaming communication interface for FX3 bridge chip and memory-mapped input and output interface for user design circuit. The ZestSC3 board with Cypress FX3 USB 3 bridge chip and Xilinx Artix FPGA(XC7A35T-1C5G3241) was used to implement FPGA verification system. It was verified that the FPGA verification system for user design circuit operated correctly under various clock frequencies using GUI software developed by visual C# and C++ DLL. The designed slave FIFO interface for FPGA verification system has modular structure and can be applicable to the different user designs with memory-mapped I/O interface.