• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.12
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• pp.1914-1919
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• 2021

With the development of advanced industries, research on image processing hardware is essential, and timing verification at the gate level is required for actual chip operation. For FPGA-based verification, DDR3 memory interface was previously applied. But recently, as the FPGA specification has improved, DDR4 memory is used. In this case, when a previously used memory interface is applied, the timing mismatch of signals may occur and thus cannot be used. This is due to the difference in performance between CPU and memory. In this paper, the problem is solved through state optimization of the existing interface system FSM. In this process, data read speed is doubled through AXI Data Width modification. For actual case analysis, ZC706 using DDR3 memory and ZCU106 using DDR4 memory among Xilinx's SoC boards are used.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.128-131
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• 2000

In this paper, the animated simulation system (Anisim) is proposed in order to develope an efficient functional system verification tool. It displays the simulation results of the designed system using graphic animation with various models lot the target system. With simple interface definitions given by the user, Anisim generates interface codes automatically. Users can describe and model the target system with the generated interface codes. Since the simulation engine is implemented in C-language, modeling is very simple and simulation can be performed in real time.

• Journal of the Korean Society of Safety
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• v.10 no.3
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• pp.21-29
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• 1995

The automotive transmission is the principal component of the power transmission system which converts the engine power into the adjustable power for the vehicle driving system. To the unskilled driver the automization of transmission is required for the safety and fuel economy. In this study, the dynamic model of the automotive power transmission system was presented and simulation program and interface board which interface IBM-PC with ECU was devloped. Through the traveling simulation by interfacing ECU with simulation program, the shifting transients are investigated. For verification of simulation experiment was carried out, the results of simulation was agreed well with those of simulation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.2
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• pp.409-416
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• 1996

This paper describes the simulation environment that verifies whether a new microporcessor described with HDL is compatible with an existing microprocessor. The compatibility verification is done by showing that the new microprocessor executes the OS(Operating System) program used in the existing microprocessor without any modification of its binary code. The proposed verification environment consists of a virtual system and a graphic user interface (GUI) module. Each module is independently designed based on serve-client model and three exists a communication part for information interchange between the two modules. This paper describes the method of constructing the verification environment and presents the compatibility verification environment of the x86 microprocessor as the simulation result.

• Journal of Computing Science and Engineering
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• v.11 no.1
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• pp.9-23
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• 2017

NuDE 2.0 (Nuclear Development Environment 2.0) is a formal-method-based software development, verification and safety analysis environment for safety-critical digital I&Cs implemented with programmable logic controller (PLC) and field-programmable gate array (FPGA). It simultaneously develops PLC/FPGA software implementations from one requirement/design specification and also helps most of the development, verification, and safety analysis to be performed mechanically and in sequence. The NuDE 2.0 now consists of 25 CASE tools and also includes an in-depth solution for indirect commercial off-the-shelf (COTS) software dedication of new FPGA-based digital I&Cs. We expect that the NuDE 2.0 will be widely used as a means of diversifying software design/implementation and model-based software development methodology.

• Journal of the Korea Society of Computer and Information
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• v.14 no.5
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• pp.55-64
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• 2009

In this paper, we design and implement verification and interface application for interactive data broadcasting middleware. This application implements ACAP and OCAP verification item according to their types (format, protocol. resource, presentation). Therefore, using this application, we can verify whether digital settop-boxes used in digital terrestrial television and digital cable television conforms to the ACAP and OCAP standards. In this paper, we evaluate our proposed application using TVPLUSiTM verifier which can verify interactive TV application in real broadcasting environment. Through performance evaluation, we show that the DTB-H650F set-top-box supports OCAP and ACAP standard 80% and 95%, respectively.

• Journal of the Ergonomics Society of Korea
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• v.18 no.3
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• pp.153-169
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• 1999

The design of nuclear control room is advancing toward totally computer based human system interfaces (HSI). Computer based interfaces offer the opportunity to provide improved support of operator performance, but if not properly deployed, can introduce new challenges. This paper reviews the Westinghouse AP-600 Human Factors Verification and Validation Plan selected for HSI evaluation model of Korea next generation nuclear control rooms. The AP-600 HSI evaluation model addressed 15 evaluation issues considering major activity class of operator and task complexity factors. This paper also describes the test procedures experimenters should follow to evaluate the addressed issues.

• 유공압시스템학회:학술대회논문집
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• 2010.06a
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• pp.56-61
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• 2010

Simulator is a development equipment which enables the ECU to operate in normal mode by simulating the interface signal between ECU and mechanical system electrically. Embedded simulator means simulation function is embedded in ECU firmware, hence the electrical signal interface is replaced by the substitution of information at system program level. This paper explains the development of embedded transmission simulator for the verification of TCU firmware function which covers shifting control and on-board diagnosis. The embedded simulation program is executed in TCU processor along with the TCU firmware and it provides TCU firmware with not only the speed information those are appropriate both in driving and shifting conditions, but also the fault detection signals. Experimental results show that the validity of embedded simulator and its usefulness to the TCU firmware development and verification.

• Journal of IKEEE
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• v.18 no.3
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• pp.341-348
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• 2014

When several resuable semiconductor IPs are connected and implemented into an integrated chip, each semiconductor IP should provide code files for synthesis and interface modeling files for simulation and verification. However, description methods and levels of abstraction of interface modeling files are different because these semiconductor IPs are designed by different designers, which makes some problems in simulation and verification. This paper proposes a standardized modeling method of semiconductor IP interfaces. It restricts semiconductor IP interfaces to several predefined level of abstraction. The proposed method helps the chip integration designer to easily connect different semiconductor IPs and to simulate and verify them.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.990-994
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• 2003

This paper describes the VoIP(Voice over Internet Protocol) SoC(System on Chip) Design and the test board development for the function verification to support voice communication services using Internet. To implement the simple system of configuration, we designed the VoIP SoC which have ARM922T of 32bit microprocessor, IP network interface, voice signal interface, various user interface function. Also we developed test program and communication protocol to verify the function of this chip. We used several tools of design and simulation, developed and tested a test board with Excalibur which includes ARM922T microprocessor and FPGA.