• 한국통신학회논문지
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• 제12권4호
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• pp.357-364
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• 1987

본 논문에서는 다중프로세서 시스템을 구성하는 중요한 요소인 다단상호결합 네트웍의 성능을 고찰한다. Baseline 네트웍을 이용한 Star네트웍 시스템의 Hardware적인 구성을 고찰하며 Analytical Model로 Request가 받아들여질 확률과 Clustering 확률을 구한다. 그리고 Baseline네트웍 대신에 Delta네트웍을 이용하여 위에서 언급한 확률을 구한 다음 네트웍의 성능을 비교한다.

• ETRI Journal
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• 제41권5호
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• pp.670-683
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• 2019

In this paper, we analyzed the signal integrity of a system interconnection module for a proposed high-density server. The proposed server integrates several components into a chassis. Therefore, the proposed server can access multiple computing resources. To support the system interconnection, among the highly integrated computing resources, the interconnection module, which is based on Serial RapidIO, has been newly adopted and supports a bandwidth of 800 Gbps while routing 160 differential signal traces. The module was designed for two different stack-up types on a printed circuit board. Each module was designed into 12- (version 1) and 14-layer (version 2) versions with thicknesses of 1.5T and 1.8T, respectively. Version 1 has a structure with two consecutive high-speed signal-layers in the middle of two power planes, whereas Version 2 has a single high-speed signal placed only in the space between two power planes. To analyze the signal integrity of the module, we probed the S-parameters, eye-diagrams, and crosstalk voltages. The results show that the high-speed signal integrity of Version 2 has a better quality than Version 1, even if the signal trace length is increased.

• 조명전기설비학회논문지
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• 제21권3호
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• pp.107-116
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• 2007

정부의 신 재생 에너지 관련 정책으로 인해 앞으로 국내에서 신 재생에너지원은 보급은 증가할 것으로 예상된다. 신 재생에너지원은 전원의 특성상 전력계통에 연계되어 운전하는 것이 일반적이지만 이러한 연계 운전은 전력계통 계획 및 운영상에 상당한 영향을 미치게 된다. 기존 배전계통의 전력조류는 변전소에서 수용가를 향한 단방향이며 이를 기반으로 계통운영이 이루어지고 있으나, 신 재생에너지원의 연계로 배전계통에 양방향의 전력조류가 형성되므로 기존의 보호시스템의 신뢰성 및 전력품질이 저하될 수 있다. 따라서 신 재생에너지원의 연계평가에 대한 기술적 평가절차가 필요하다. 본 논문에서는 국내 배전계통의 전형적인 보호기기인 자동 재폐로 차단기와 구분개폐기의 특성을 살펴보고, 현재의 자동재폐로 차단기-구분개폐기 보호시스템에서 분산전원의 연계용량을 검토하는 방안을 제시하고자 한다.

• 전기학회논문지
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• 제57권4호
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• pp.629-634
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• 2008

In this paper, we propose a simple numerical formula which can estimate the additional delay time due to interconnection branches in general source-termination scheme. We show that interconnection branches have influence on both signal quality and time delay. Using the proposed numerical formula, time delay can be easily predicted by system designers.

• 한국전자파학회논문지
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• 제7권5호
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• pp.395-407
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• 1996

In this paper, we describe the crossover of the parasitic capacitance at the interconnections for the system miniature, analyse ground capacitance and mutual capacitance due to actually coupled line in the ICs or MCMs. From the results of deviding interconnection line with infinite parts, using Green's function with image charge method and moments, we could obtain 70% decrease of system runtime parasitic inductance because of simplicity of transforming formular.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 하계학술대회 논문집 A
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• pp.311-313
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• 2003

There have been public attraction and studies about distributed generation systems. But protective relay must be installed between utility system and customer owned distributed generation system has not been developed. So this paper describes the development of a digital protective relay for interconnection. The developed protective relay includes protective elements required by KEPCO at the interconnection point.

• 조명전기설비학회논문지
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• 제28권9호
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• pp.83-88
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• 2014

When DG interconnection into network is examined, details of the review are overvoltage, protective device malfunction, etc. In the case of protective device malfunction, replacing protective device into bi-directional protective device and installation NGR are the solution. Overvoltage at interconnection point occurs because the load is relatively less than DG output. When overvoltage at interconnection point occurs, DG interconnection is not permitted because this overvoltage affect other customers. Interconnection by installation new distribution line is one solution but it costs much money. Without installation new investment, change of NOP(Normal Open Point) position is a possible solution about DG interconnection into network.

• 한국정보통신학회논문지
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• 제18권7호
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• pp.1727-1733
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• 2014

본 논문에서는 지능형 홈 네트워크 디바이스간의 상호연동 미들웨어 Adaptor를 설계하였다. 홈 네트워크 상호연동 미들웨어 Adaptor는 UPnP, LonWorks, LnCP, HAVi 등 다양한 형태의 미들웨어가 존재하고, 다수의 미들웨어를 연동하기 위해서는 기존 시스템을 수정이 필요하지만, 본 논문에서 설계한 상호연동 미들웨어 Adaptor는 다수의 미들웨어를 기존 시스템에 별도의 수정 없이 연동이 가능하도록 설계하였다. 설계한 상호연동 미들웨어 Adaptor에 대한 성능을 평가하기 위해 다양한 업체에서 생산한 디바이스를 이용하여 실험 장치를 구현하였고, 개발한 상호연동 미들웨어 Adaptor가 내장된 모바일 앱 프로그램을 개발하여 성능을 평가하였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1992년도 하계학술대회 논문집 A
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• pp.126-129
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• 1992

Compared to other sources of electricity such as Thermal and Nuclear power plant, dispersed storage and generation system (DSG) is environmentally clean, quiet and efficient, thus this source is expected to be introduced In urban area by the utilities and customers. If a great number of DSG will be applied to electric power system in the rear future (around 2000, in Korea), these will give a great influence on the existing power system. In other words, the interconnection to electric power system of these source may bring many problems such as system operation, protection coordination, and service quality related with voltages (110${\pm}$6V, 220${\pm}$13V), harmonics (5%) and pour factor (90% over). So, this analysis of the interconnection to power system of DSG is required

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.823-826
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• 2003

FPGA-based logic emulator with lane gate capacity generally comprises a large number of FPGAs connected in mesh or crossbar topology. However, gate utilization of FPGAs and speed of emulation are limited by the number of signal pins among FPGAs and the interconnection architecture of the logic emulator. The time-multiplexing of interconnection wires is required for multi-FPGA system incorporating several state-of-the-art FPGAs. This paper proposes a circuit partitioning algorithm called SCATOMi(SCheduling driven Algorithm for TOMi)for multi-FPGA system incorporating four to eight FPGAs where FPGAs are interconnected through TOMi(Time-multiplexed, Off-chip, Multicasting interconnection). SCATOMi improves the performance of TOMi architecture by limiting the number of inter-FPGA signal transfers on the critical path and considering the scheduling of inter-FPGA signal transfers. The performance of the partitioning result of SCATOMi is 5.5 times faster than traditional partitioning algorithms. Architecture comparison show that the pin count is reduced to 15.2%-81.3% while the critical path delay is reduced to 46.1%-67.6% compared to traditional architectures.