• Transactions of the Korean Society of Mechanical Engineers A
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• v.28 no.12
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• pp.1856-1863
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• 2004

In the last 50 years, lead-contained solder materials have been the most popular interconnect materials used in the electronics industry. Recently, lead-free solders are about to replace lead-contained solders for preventing environmental pollutions. However, the reliability of lead-free solders is not yet satisfactory. Several researchers reported that lead-contained solders have a good fatigue property. The others published that the lead-free solders have a longer thermal fatigue life. In this paper, the reason for the contradictory results published on the estimation of fatigue life of lead-free solder is investigated. In the present study, fatigue behavior of 63Sn37Pb, and two types of lead-free solder joints were compared using pseudo-power cycling testing method, which provides more realistic load cycling than chamber cycling method does. Pseudo-power cycling test was performed in various temperature ranges to evaluating the shear strain effect. A nonlinear finite element model was used to simulate the thermally induced visco-plastic deformation of solder ball joint in BGA packages. It was found that lead-free solder joints have a good fatigue property in the small temperature range condition. That condition induce small strain amplitude. However in the large temperature range condition, lead-contained solder joints have a longer fatigue life.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2001.07a
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• pp.100-103
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• 2001

In this study, the adhesion and thermal property of the electroless-deposited Cu thin film were investigated. The multilayered structure of Cu/TaN/Si was fabricated by electroless-depositing the Cu thin layer on the TaN diffusion barrier which was deposited by MOCVD on the Si substrate. The thermal stability was investigated by measuring the resistivity as post-annealing temperature far the multilayered Cu/TaN/Si specimen which was annealed at Ar gas. The adhesion property of Cu 171ms was evaluated by the scratch test. The adhesion of the electroless-deposited Cu film was compared with other deposition methods of thermal evaporation and sputtering. The scratch test showed that the adhesion of electroless plated Cu film on TaN was better than those of sputtered Cu film and evaporated Cu film.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.9
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• pp.1638-1643
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• 2010

HVDC is better economic method than HVAC in case of long distance transmission and it is possible to interconnect transmission lines regardless of difference of power frequency. The electrical environment problems of HVDC overhead transmission line are electric field, charged voltage, ion current and so on. For biopolar HVDC lines, most of the ions are directed toward the opposite polarity conductor, but a significant fraction is also directed toward the ground. These problems are major factor to design configuration of HVDC overhead transmission line. Therefore, It is necessary to test an environmental characteristics of HVDC overhead transmission line. In this paper, to assess the ion characteristic of HVDC transmission line, continuous measurements have been done on the biopolar single circuit line with ACSR 480mm2-6 bundle conductors of Gochang HVDC Test line. And then the ion characteristics were analyzed.

• 한국신재생에너지학회:학술대회논문집
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• 2007.06a
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• pp.121-124
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• 2007

Stacks of solid oxide fuel cell under 1kW max power were designed on planar type employing anode supported cell and metallic interconnects. The stacks composed of 3-cells, 8-cells, and 16-cells were fabricated by using single cell purchased from Indec, sealant and interconnect prepared at RIST. In performance test of the final 16-cells stacks, OCV was recorded to be 16.7 V. Peak power and power density were 1 kW, 0.77 $W/cm^{2}$ at $820^{\circ}C$, respectively. In addition, the long term degradation rate of the power exhibited 2.25 % in 500 h at $750^{\circ}C$.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.2
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• pp.88-93
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• 2004

We, for the first time, present novel test patterns and conclusive on-chip data indicating that the variation of coupling capacitance, ${\Delta}C_C$ by crosstalk can be larger than static coupling capacitance, $C_C$. The test chip is fabricated using a generic 150 nm CMOS technology with 7 level metallization. It is also shown that ${\Delta}C_C$ is strongly dependent on the phase of aggressive lines. For antiphase crosstalk ${\Delta}C_C$ is always larger than $C_C$ while for in-phase crosstalk $D_{\Delta}C_C$is smaller than $C_C$.

• Journal of Welding and Joining
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• v.31 no.6
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• pp.77-83
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• 2013

3D packaging technology using TSV (Through Silicon Via)has been studied in the recent years to achieve higher performance, lower power consumption and smaller package size because electrical line is shorter electrical resistivity than any other packaging technology. To stack TSV chips vertically, reliable and robust bonding technology is required because mechanical stress and thermal stress cause fracture during the bonding process. Cu pillar/solder ${\mu}$-bump bonding process is usually to interconnect TSV chips vertically although it has weak shape to mechanical stress and thermal stress. In this study, we suggest Insert-Bump (ISB) bonding process newly to stack TSV chips. Through experiments, we tried to find optimal bonding conditions such as bonding temperature and bonding pressure. After ISB bonding, we observed microstructure of bump joint by SEM and then evaluated properties of bump joint by die shear test.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.41 no.4
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• pp.41-49
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• 2004

In this paper, a design and measurement method for FPGA embedded gigabit-transceiver is presented. Altera's Stratix GX device which is general purpose transceiver called GXB was used for implementing PCI Express transceiver. PCI Express is the generation high performance serial I/O bus used to interconnect peripheral devices. After GXB was set follow by PCI Express specifications, the design has been verified by timing simulation and implemented as hardware. We tested it as follow. First GXB internal digital and analog block test second GXB transmitter signal integrity test called Eye mask test, third GXB high-speed serial I/O buffer and on-chip termination test and the last GXB protocol test. This paper shows all the design and measurement procedure about FPGA embedded gigabit-transceiver.

• Journal of the Microelectronics and Packaging Society
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• v.6 no.1
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• pp.31-37
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• 1999

In this study, the thermal property and adhesion of the electroless-deposited Cu thin film were investigated. The multilayered structure of Cu /TaN /Si was fabricated by electroless-depositing the Cu thin layer on the TaN diffusion barrier which was deposited by MOCVD on the Si substrate. The thermal stability was investigated by measuring the resistivity as post-annealing temperature for the multilayered Cu /TaN /Si specimen which was annealed at atmospheres of $H_2$and Ar gases, respectively. The adhesion strength of Cu films was evaluated by the scratch test. The adhesion of the electroless-deposited Cu film was compared with other deposition methods of thermal evaporation and sputtering. The scratch test showed that the adhesion of electroless plated Cu film on TaN was better than that of sputtered Cu film and evaporated Cu film.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.15 no.6
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• pp.150-158
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• 2016

This paper is on a design of a new balise system which has a new functional part of a micro-power inductive wireless loop vehicle detector. The field test has processed and the data has analyzed for check the solar energy operable ability of the detect data interconnect sub-system which includes repeaters and field controllers. Instead of a railroad environment, 12 individual parking-lots are used for field test environment. As a result, in the condition of the designed system and the test environment, it is assumed that under 200 passing vehicles(train or tram) per day can be processed only with solar energy.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.4
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• pp.229-236
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• 2005

This paper presents a system level architecture evaluation technique that leverages transaction level modeling but also significantly extends it to the realm of system level performance evaluation. A major issue lies with the modeling effort. To reduce the modeling effort the proposed technique develops the concept of worst case scenarios. Since the memory controller is often found to be an important component that critically affects the system performance and thus needs optimization, the paper further addresses how to evaluate and optimize the memory controllers, focusing on the test environment and the methodology. The paper also presents an industrial case study using a real state-of-the-art design. In the case study, it is reported that the proposed technique has helped successfully find the performance bottleneck and provide appropriate feedback on time.