• Journal of the Institute of Electronics Engineers of Korea SD
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• 제42권5호
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• pp.47-54
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• 2005

In this paper, novel test patterns and on-chip data are presented to indicate that the variation of coupling capacitance, ${\Delta}Cc$ by crosstalk can be larger than static coupling capacitance, Cc. It is also shown that ${\Delta}Cc$ is strongly dependent on the phase of aggressive lines. for anti-phase crosstalk ${\Delta}Cc$ is always larger than Cc while for in-phase crosstalk ${\Delta}Cc$ is smaller than Cc. HSPICE simulation shows good agreement with the measurement data.

• Journal of the Korean Ceramic Society
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• 제42권12호
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• pp.833-841
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• 2005

The oxidation resistance and electrical conductivity of various commercial ferritic stainless steels including STS444 were tested in an air atmosphere at $700^{\circ}C$. Crofer22 developed specially for SOFC interconnect was also examined for the aim of comparing with the test results of STS444. Although STS444 exhibited higher oxidation resistance than Corfer22, the electrical conductivity of the scale formed on Crofer22 was higher, indicating that the resistivity of scale formed on Crofer22 is much lower than that of STS444. To gain a better understanding of the relation between oxidation behavior and electrical conductivity, the oxide scales formed on STS444 and Crofer22 were analyzed in terms of the structure, composition, and phase. Consequently, the influence of alloying elements on electrical conductivity of Fe-Cr alloys was discussed.

• Journal of the Microelectronics and Packaging Society
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• 제20권3호
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• pp.1-6
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• 2013

3D integrated circuit(IC) technology with TSV(through Si via) liquid cooling system is discussed. As a device scales down, both interconnect and packaging technologies are not fast enough to follow transistor's technology. 3D IC technology is considered as one of key technologies to resolve a device scaling issue between transistor and packaging. However, despite of many advantages, 3D IC technology suffers from power delivery, thermal management, manufacturing yield, and device test. Especially for high density and high performance devices, power density increases significantly and it results in a major thermal problem in stacked ICs. In this paper, the recent studies of TSV liquid cooling system has been reviewed as one of device cooling methods for the next generation thermal management.

• Transactions of the Korean Society of Automotive Engineers
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• 제13권6호
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• pp.48-55
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• 2005

In this paper, a mathematical model and a simulation method for the response time analysis of Local Interconnect Network(LIN) based network systems are proposed. Network-induced delays in a network based control system can vary widely according to the transmission time of message and the overhead time of transmission. Therefore, in order to design a distributed control system using LIN network, a method to predict and verify the timing behavior of LIN protocol is required at the network design phase. Furthermore, a simulation environment based on a timing model of LIN protocol is beneficial to predict the timing behavior of LIN. The model equation is formulated with six timing parameters deduced from timing properties of LIN specification. Additionally, LIN conformance test equations to verify LIN device driver are derived with timing constraints of the parameters. The proposed model equation and simulation method are validated with a result that is measured at real LIN based network system.

• Journal of Electrical Engineering and information Science
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• 제2권5호
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• pp.17-26
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• 1997

Interconnect characterization on a wafer level was performed. Test patterns for single, two-coupled, and triple-coupled lines ere designed by using 0.5$\mu\textrm{m}$ CMOS process. Then interconnect capacitances and resistances were experimentally extracted by using tow port network measurements, Particularly to eliminate parasitic effects, the Y-parameter de-embedding was performed with specially designed de-embedding patterns. Also, for the purpose of comparisons, capacitance matrices were calculated by using the existing CAD model and field-solver-based commercial simulator, METAL and MEDICI. This work experimentally verifies that existing CAD models or parameter extraction may have large deviation from real values. The signal transient simulation with the experimental data and other methodologies such as field-solver-based simulation and existing model was performed. as expected, the significantly affect on the signal delay and crosstalk. The signal delay due to interconnects dominates the sub-micron-based a gate delay (e.g., inverter). Particularly, coupling capacitance deviation is so large (about more than 45% in the worst case) that signal integrity cannot e guaranteed with the existing methodologies. The characterization methodologies of this paper can be very usefully employed for the signal integrity verification or he electrical design rule establishments of IC interconnects in the industry.

• Journal of the Korean Society for Aviation and Aeronautics
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• 제15권1호
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• pp.61-67
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• 2007

The importance and cost of avionics system in the integration of an aircraft is continuously increasing. And we can expect enlarged software portion in the system integration for the more intelligent, reliable, and automated avionics system. Both military and commercial avionics community have moved toward commercial-off-the-shelf(COTS) equipment and open systems architecture not only to increase affordability but also to reduce acquisition cost, shorten development time and risk. The same concept is applied in developing avionics test system used for the avionics system integration test. In this paper, we present important topics in the development of avionics system including real-time operating system, interconnect data bus, software development methodology, software development process, and system integration test.

• Journal of the Microelectronics and Packaging Society
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• 제28권1호
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• pp.39-46
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• 2021

The quantitative measurement of interfacial adhesion energy (Gc) of multilayer thin films for Cu interconnects was investigated using a double cantilever beam (DCB) and 4-point bending (4-PB) test. In the case of a sample with Ta diffusion barrier applied, all Gc values measured by the DCB and 4-PB tests were higher than 5 J/㎡, which is the minimum criterion for Cu/low-k integration without delamination. However, in the case of the Ta/Cu sample, measured Gc value of the DCB test was lower than 5 J/㎡. All Gc values measured by the 4-PB test were higher than those of the DCB test. Measured Gc values increase with increasing phase angle, that is, 4-PB test higher than DCB test due to increasing plastic energy dissipation and roughness-related shielding effects, which matches well interfacial fracture mechanics theory. As a result of the 4-PB test, Ta/Cu and Cu/Ta interfaces measured Gc values were higher than 5 J/㎡, suggesting that Ta is considered to be applicable as a diffusion barrier and a capping layer for Cu interconnects. The 4-PB test method is recommended for quantitative adhesion energy measurement of the Cu interconnect interface because the thermal stress due to the difference in coefficient of thermal expansion and the delamination due to chemical mechanical polishing have a large effect of the mixing mode including shear stress.

• Journal of the Institute of Electronics Engineers of Korea SD
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• 제41권8호
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• pp.9-16
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• 2004

For a System-on-a-Chip(SoC) comprised of multiple IP cores, test control techniques have been developed to perform the internal and external test efficiently relying on the various design for testability techniques such as scan and BIST(Built-In Self-Test). However the test area overhead is too expensive to guarantee diverse test link configurations. In this paper, at first we introduce a new flag based Wrapped Core Linking Module(WCLM) that enables systematic integration of IEEE 1149.1 TAP'd cores and P1500 wrapped cores. Then a simple test control technique, which can interconnect internal scan chains of different cores, is described with requiring least amount of area overhead compared with other state-of-art techniques. The design preserves compatibility with standards and scalability for hierarchical access.

• Journal of the Institute of Electronics and Information Engineers
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• 제50권1호
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• pp.131-136
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• 2013

TSV based 3D ICs have been widely developed with new problems at die and IC levels. It is imperative to test at post-bond as well as pre-bond to achieve high reliability and yield. This paper introduces a new testable design technique which not only test microscopic defects at TSV input/output contact at a die but also test interconnect defects at a stacked IC. IEEE 1500 wrapper cells are augmented and through at-speed tests for pre-bond die and post-bond IC, known-good-die and defect free 3D IC can be massively manufactured+.

• ETRI Journal
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• 제38권3호
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• pp.479-486
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• 2016

System-on-chip (SoC) designs have a number of flip-flops; the more flip-flops an SoC has, the longer the associated scan test application time will be. A scan shift operation accounts for a significant portion of a scan test application time. This paper presents physical-aware approaches for speeding up scan shift operations in SoCs. To improve the speed of a scan shift operation, we propose a layout-aware flip-flop insertion and scan shift operation-aware physical implementation procedure. The proposed combined method of insertion and procedure effectively improves the speed of a scan shift operation. Static timing analyses of state-of-the-art SoC designs show that the proposed approaches help increase the speeds of scan shift operations by up to 4.1 times that reached under a conventional method. The faster scan shift operation speeds help to shorten scan test application times, thus reducing test costs.