• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.1
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• pp.8-16
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• 2020

In this paper, a single-bit 2nd-order delta-sigma modulator with the architecture of cascaded-of-integrator feedforward (CIFF) is proposed for column-parallel analog-to-digital converter (ADC) array used in a low noise CMOS image sensor. The proposed modulator implements two switched capacitor integrators and a single-bit comparator within only 10-㎛ column-pitch for column-parallel ADC array. Also, peripheral circuits for driving all column modulators include a non-overlapping clock generator and a bias circuit. The proposed delta-sigma modulator has been implemented in a 110-nm CMOS process. It achieves 88.1-dB signal-to-noise-and-distortion ratio (SNDR), 88.6-dB spurious-free dynamic range (SFDR), and 14.3-bit effective-number-of-bits (ENOB) with an oversampling ratio (OSR) of 418 for 12-kHz bandwidth. The area and power consumption of the delta-sigma modulator are 970×10 ㎛2 and 248 ㎼, respectively.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.16 no.6
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• pp.51-59
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• 2002

This paper deals with the measurement and analysis of the induced voltages and magnetic fields caused by the operation of home appliances. The induced voltage and magnetic field measurement circuit used in this work consists of the induction coil, the operational preamplifier and the active integrator. Television set and monitors for personal computer cause strong magnetic fields rich in harmonics and high induced voltages by using the switching power suppliers. The strong magnetic field intensity and high induced voltage were created by 14" television set, and their values are 2.1 ［$\mu$Tp-p］and 140 ［mVp-p］at the distance of 0.4 ［m］, respectively. However, the induced voltage per unit magnetic field intensity was created by 17" monitor for personal computer and the measured data was approximately 560［mV/$\mu$T］at the same distance. distance.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.9
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• pp.800-807
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• 2006

To enhance the conversion speed more fast, we separate the determination process of MSB and LSB with the two independent ADC circuits of the Incremental Sigma Delta ADC. After the 1st Incremental Sigma Delta ADC conversion finished, the 2nd Incremental Sigma Delta ADC conversion start while the 1st Incremental Sigma Delta ADC work on the next input. By determining the MSB and the LSB independently, the ADC conversion speed is improved by two times better than the conventional Extended Counting Incremental Sigma Delta ADC. In processing the 2nd Incremental Sigma Delta ADC, the inverting sample/hold circuit inverts the input the 2nd Incremental Sigma Delta ADC, which is the output of switched capacitor integrator within the 1st Incremental Sigma Delta ADC block. The increased active area is relatively small by the added analog circuit, because the digital circuit area is more large than analog. In this paper, a 14 bit Extended Counting Incremental Sigma-Delta ADC is implemented in $0.25{\mu}m$ CMOS process with a single 2.5 V supply voltage. The conversion speed is about 150 Ksamples/sec at a clock rate of 25 MHz. The 1 MSB is 0.02 V. The active area is $0.50\;x\;0.35mm^{2}$. The averaged power consumption is 1.7 mW.

• Journal of IKEEE
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• v.26 no.2
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• pp.299-305
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• 2022

Analog-digital converter (ADC) should be one of the most important blocks that convert various physical signals to digital ones for signal processing in the digital signal domain. As most operations of the analog circuit for sensor signal processing have been replaced by digital circuits, high-resolution performance is required for ADC. In addition, low-power must be the critical issue in order to extend the battery time of mobile system. The existing integrating sigma-delta ADCs has a characteristic of high resolution, but due to its low supply voltage condition and advanced technology, circuit error and corresponding resolution degradation of ADC result from the finite gain of the operational amplifier in the integrator. Buffer compensation technique can be applied to minimize gain errors, but there is a disadvantage of additional power dissipation due to the added buffer. In this paper, incremental signal-delta ADC is proposed with buffer switching scheme to minimize current and igh-pass bias circuit to improve the settling time.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.3
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• pp.184-196
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• 2020

In this paper, a single-bit 2nd-order delta-sigma modulator with the architecture of cascaded-of-integrator feedforward (CIFF) is proposed for precision measurement of current flowing through a secondary cell battery in a battery management system (BMS). The proposed modulator implements two switched capacitor integrators and a single-bit comparator with peripheral circuits such as a non-overlapping clock generator and a bias circuit. The proposed structure is designed to be applied to low-side current sensing method with low common mode input voltage. Using the low-side current measurement method has the advantage of reducing the burden on the circuit design. In addition, the ±30mV input voltage is resolved by the ADC with 15-bit resolution, eliminating the need for an additional programmable gain amplifier (PGA). The proposed a single-bit 2nd-order delta-sigma modulator has been implemented in a 350-nm CMOS process. It achieves 95.46-dB signal-to-noise-and-distortion ratio (SNDR), 96.01-dB spurious-free dynamic range (SFDR), and 15.56-bit effective-number-of-bits (ENOB) with an oversampling ratio (OSR) of 400 for 5-kHz bandwidth. The area and power consumption of the delta-sigma modulator are 670×490 ㎛2 and 414 ㎼, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.121-126
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• 2007

This paper describes a 9.09 Gb/s CMOS demultiplexer using redundant multi-valued logic (RMVL). The proposed circuit receives serial binary data and is converted to parallel redundant multi-valued data using RMVL. The converted data are reconverted to parallel binary data. By the redundant multi-valued data conversion, the RMVL makes it possible to achieve higher operating speeds than that of a conventional binary logic. The implemented demultiplexer consists of eight integrators. Each integrator is composed of an accumulator, a window comparator, a decoder and a D flip flop. The demultiplexer is designed with Samsung $0.35{\mu}m$ standard CMOS process. The validity and effectiveness are verified through the post layout simulation. The demultiplexer is achieved the maximum data rate of 9.09 Gb/s and the average power consumption of 69.93 mW. This circuit is expected to operate at higher speed than 9.09 Gb/s in the deep-submicron process of the high operating frequency.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.11
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• pp.2081-2093
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• 1994

In this study, we design and implement 64 QAM demodulator which has 155 Mbps, first level of CCITT G707 SDH(Synchronous Digital Hierachy) for STM 1 signal transmission. Carrier recovery which effects the demodulator performance uses decision feedback carrier using 8 bits A/D converter. Also, PSF(Pulse Shaping Filter) is 7 order elliptic filter. Carrier recovery circuit is designed and implemented digital type which use high 3 bits of 8 bits conversion data as data and the order low bits as error data and hybrid type which use VCO and analog integrator. Therefore we obtain stable performance recovery.

• 제어로봇시스템학회:학술대회논문집
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• 1993.10b
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• pp.339-344
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• 1993

An H$_{\infty}$ control system design for a magnetic levitation system is presented. In the control system design, we consider the influence of both disturbances and uncertainties in the model. The main disturbances stem from the position sensors.The uncertainties are divided into electromagnetic and mechanical ones: the former are due to the gain change in the current amplifier, the influence of leakage flux and modelling error in the magnetic circuit and the latter are due to the changes of the mass and the moments of inertia of the vehicle. Therefore, the designed controller is indispensable to guarantee the robustness of this system for both stability and performance. The controller design is based on the standard H$_{\infty}$ optimal control problem. As the novel features in this paper :(1) there are two poles on j.omega.-axis in the control model;(2) an integrator is included in the controller so that equivalently there are three poles on j.omega.-axis in the model. Finally, several experiments and simulations are carried out to verify the high performance and robustness of the designed control system.m.

• Progress in Superconductivity
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• v.5 no.1
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• pp.31-37
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• 2003

Wide-bandwidth SQUID current amplifier and its control electronics have been constructed for detecting pulse outputs of a superconducting microcalorimeter. The current amplifier made of a double relaxation oscillation SQUID (DROS) has a bandwidth of 1.2 MHz and typical white noise level of about 6 pA/(equation omitted) Hz. To increase the dynamic range of the current amplifier, the flux-locked loop (FLL) has additional circuits to reset the integrator and to count reset numbers which present the number of passed flux quanta. In this system, dynamic range covers from -65 mA to +65 mA. SQUID electronics are controlled by software to get the optimum FLL condition, and to control the current to bias the transition edge sensor (TES). The electronics are shielded from the outside electromagnetic noises by using an aluminum case of 66 mm ${\times}$ 25 mm ${\times}$ 100 mm, and consist of 2 separate printed-circuit-boards for the current amplifier and the control electronics, respectively. The SQUID current amplifier and its control electronics will be used in TESs for detecting photons such as UV and X-ray with high energy resolution.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.43 no.1 s.307
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• pp.39-44
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• 2006

Pattern noise in the Delta-Sigma modulator is a well Known phenomenon that intrigued many circuit designers. These noise appear as the modulator output falls into a cyclic mode of operation. This paper addresses the dependence of these tone signal upon the system topologies. Among the four well known single-stage DSM topologies, namely Cascade of Integrators with Feedback Form(CIFB), Cascade of Integrators with Feedforward Form(CIFF), Cascade of Resonators with Feedback Form(CRFB), and Cascade of Resonators with Feedforward Form(CRFF), resonator type DSMs turn out to be more susceptible to the pattern noise than the integrator type. Noise transfer functions of the investigated topologies are also presented.