• IEIE Transactions on Smart Processing and Computing
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• 제4권3호
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• pp.152-157
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• 2015

Various power supply noise sources in a system integrated circuit degrade the performance of a low dropout (LDO) regulator. In this paper, a capacitor-less low dropout regulator for enhanced power supply rejection is proposed to provide good power supply rejection (PSR) performance. The proposed scheme is implemented by an additional capacitor at a gate node of a pass transistor. Simulation results show that the PSR performance of the proposed LDO regulator depends on the capacitance value at the gate node of the pass transistor, that it can be maximized, and that it outperforms a conventional LDO regulator.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1991년도 추계학술대회 논문집 학회본부
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• pp.219-222
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• 1991

It is difficult to adapt modern control theory to power conversion system for the price of real time control H/W and the difficulty of S/W implementation. But recent development of large integrated circuit make it possible that One-Chip microprocessor processes high speed arithmatic calculation used in control theory. Specially this chip is called Digital Signal Processing chip. So, this research developes high performance, high reliable digital control system using TMS320C30 of Texas Instrument for real time control in power conversion system.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2003년도 추계학술발표강연 및 논문개요집
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• pp.65-65
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• 2003

Chemical mechanical polishing (CMP) is one of the most important processes in recent ULSI (Ultra Large Scale Integrated Circuit) manufacturing technology. Recently, ceria slurries with surfactant have recently been used in STI-CMP,[1] became they have high oxide-to-nitride removal selectivity and widen the processing margin The role of the abrasives, however, on the effect of planarization on STI-CMP is not yet clear. In this study, we investigated how the crystal characteristic affects the planarization efficiency of wafer surface with controlling crystallite size and poly crystalline abrasive size independently.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1987년도 전기.전자공학 학술대회 논문집(II)
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• pp.1547-1550
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• 1987

This paper describes a new design rule checking system, PC-DRC, for CIF mask layout, which was written in C language on IBM PC/AT under DOS 3.0 environment. H/W devices and S/W utilities for PC-DRC is identical to that for PC-LADY[6], which makes PC-DRC an ideal post-processing routine for CIF file generated by PC-LADY. Various spurious errors were eliminated by ORing the input ClF data for each layer and the design rule errors were checked by edge based method on rectilinear polygon form. The detected errors are stored in CIF and displayed on CRT simultaneously.

• 한국통신학회논문지
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• 제4권1호
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• pp.25-31
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• 1979

All the resitors in the active RC filter networks can be relplaced by the switched capacitors. Therefore, An SC filter circuit can be fully integrated using MOS technology. A switched capacitor is much better than a resistor in temperature and linearity characteristics, and the former can be fabricated on the much smaller area then the latter. In this paper, It is given the generalized disign method of the active SC filter from the active RC filter using Bilinear Z-transformation. By SC filtering Techniques using Bilinear Z-transform, It enalbes us to realize the FDNR and Gyrator filters, which could not be realized in the exsisting designs, and it permits the processing of signals at much higher frequenies that many previous designs do. Experiments show that the response of the SC active filter is similiar to that of its prototype active RC filter.

• 전력전자학회:학술대회논문집
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• 전력전자학회 1999년도 전력전자학술대회 논문집
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• pp.274-277
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• 1999

The paper describes a implementation of space vector pulse-width modulation (SVPWM) voltage source inverter using Field Programmable Gate Array(FPGA) for a induction motor control system. The implemented chip is included logic circuits for SVPWM, dead time compensation and speed detection using Quick Logic, QL16X24B. The maximum operating frequency and delay time can be set to 110MHz and 6 nsec. The designed FPGA for SVPWM can be incorporated with a digital signal processing to provide a simple and effective solution for high performance voltage source inverter drives. Simulation and Implementation results are shown to verify the usefulness of FPGA as a Application Specific Integrated Circuit(ASIC) in power electronics applications

• IEIE Transactions on Smart Processing and Computing
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• 제5권2호
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• pp.123-128
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• 2016

In this paper, an inversely tapered coupler with Bragg reflectors is reported for the first time. With appropriately positioned reflecting structures, our fiber-to-chip coupler can more efficiently transmit the light from fiber to a waveguide in a photonic integrated circuit (PIC). A numerical simulation evaluated the coupler's efficiency with the reflector. Optimized parameters that maximize the efficiency of the coupler are also investigated. Simulation results show that the reflector with appropriate parameters enhances efficiency by up to 7 dB. Likewise, Bragg metal reflectors implemented by the conventional metallization process can also improve efficiency. It is also shown that the proposed reflector enhances the coupling efficiency in a double-tip taper coupler.

• 제어로봇시스템학회논문지
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• 제8권1호
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• pp.54-59
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• 2002

In the three-axis control of satellites by using on-board actuators, gyros are usually used to measure the attitude angles and angular rates. The gyros are operated by electronic parts and mechanical actuators. The digital components of the electronic parts consist of largely FPGA (Field Programmable Gate Array) as one of the methods for VLSI(Very Large Scale Integrated) circuit design, while the mechanical parts provide output signal directly by mechanical actuation of a spinning rotor. In this research, a mixed mode of gyro is implemented in FGA. In addition to the hardware implementation, the simulation study was conducted by using the SABER for the mixed mode simulator. Results for the practical implementation of the satellite ACS (Attitude Control System) interfaced with the data processing are also presented to validate the FPGA implementation.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2000년도 제15차 학술회의논문집
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• pp.30-30
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• 2000

In the three axis control of satellite by using reaction wheel and gyro, a Gyro carries out measuring of the attitude angie and the attitude angular velocity. The Gyro is operated by the electronic part and the mechanic actuator. The digital part of the electronic part is consisted of the FPGA (Field Programmable Gate Array), which is one of the methods for designing VLSI (Very Large Scale Integrated Circuit), and the mechanic actuator processes the input/output data by the dynamic model. In the research of the mixed mode of Gyro, the simulation is accomplished by SABER of the mixed mode simulator and the results for the practical implementation of the satellite ACS (Attitude Control System) interfaced with the data processing are proposed.

• 한국산업융합학회 논문집
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• 제2권2호
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• pp.103-108
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• 1999

The paper describes a implementation of space vector pulse-width modulation voltage source inverter and interfacing of DSP using field programmable gate array(FPGA) for a induction motor vector control system. The implemented chip is included logic circuits for SVPWM, dead time compensation and speed detection using Quick Logic, QLl6X24B. The maximum operating frequency and delay time can be set to 110MHz and 6 nsec. The designed Application Specific Integrated Circuit(ASIC) for SVPWM can be incorporated with a digital signal processing to provide a simple and effective solution for high performance induction motor drives with a voltage source inverter. Simulation and implementation results are shown to verify the usefulness of ASIC in a motor drive system and power electronics applications.