• Proceedings of the Korean Institute of Building Construction Conference
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• 2006.11a
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• pp.87-90
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• 2006

This study investigates the temperature history of slab mock-up specimens for hot weather concreting applying various surface insulating methods, in order to improve concrete quality at hot weather condition. Test showed that the use of insulating blanket or a bubble sheet on upper section of slab prevented from abrupt increase of temperature and vaporization of moisture during early curing at hot weather circumstance. In addition, it secured higher strength at early age. Therefore it is concluded that concrete construction insulating with the bubble sheet will reduce the plastic and drying shrinkage as well as improve strength at early age, thus securing concrete duality.

• Proceedings of the Korean Vacuum Society Conference
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• 2009.02a
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• pp.172.2-172.2
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• 2009

• Korean Journal of Materials Research
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• v.11 no.10
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• pp.900-906
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• 2001

We prepared tunnel magnetoresistance(TMR) devices of Ta($50\AA$)/NiFe($50\AA$)/IrMn(150$\AA$)/CoFe($50\AA$)/Al ($13\AA$)-O/CoFe($40\AA$)/NiFe($400\AA$)/Ta(50$\AA$) structure which has 100$\times$100 $\mu\textrm{m}^2$ junction area on $2.5\Times2.5 cm^{2}$ $Si/SiO_2$ ($1000\AA$) substrates by a inductively coupled plasma(ICP) magnetron sputter. We fabricated the insulating layer using a ICP plasma oxidation method by varying oxidation time from 80 sec to 360 sec, and measured resistances and magnetoresistance(MR) ratios of TMR devices. We used a high resolution transmission electron microscope(HRTEM) to investigate microstructural evolution of insulating layer. The average resistance of devices increased from 16.38 $\Omega$ to 1018 $\Omega$ while MR ratio decreased from 30.31 %(25.18 %) to 15.01 %(14.97 %) as oxidation time increased from 80 sec to 360 sec. The values in brackets are calculated values considering geometry effect. By comparing cross-sectional TEM images of 220 sec and 360 sec-oxidation time, we found that insulating layer of 360 sec-oxidized was 30 % and 40% greater than that of 150 sec-oxidized in thickness and thickness variation, respectively. Therefore, we assumed that increase of thickness variation with oxidation time is major reason of MR decrease. The resistance of 80 sec-oxidized specimen was 160 k$\Omega$$\mu\textrm{m}^2$ which is appropriate for industrial needs of magnetic random access memory(MRAM) application.

• 한국초전도학회:학술대회논문집
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• v.10
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• pp.165-168
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• 2000

We fabricated ramp-edge Josephson junctions with barriers formed by interface treatments instead of epitaxially grown barrier layers. A low-dielectric Sr$_2$AlTaO$_6$(SAT) layer was used as an ion-milling mask as well as an insulating layer for the ramp-edge junctions. An ion-milled YBa$_2$Cu$_3$O$_{7-x}$ (YBCO)-edge surface was not exposed to solvent through all fabrication procedures. The barriers were produced by structural modification at the edge of the YBCO base electrode using high energy ion-beam treatment prior to deposition of the YBCO counter electrode. We investigated the effects of high energy ion-beam treatment, annealing, and counter electrode deposition temperature on the characteristics of the interface-controlled Josephson junctions. The junction parameters such as T$_c$, I$_c$c, R$_n$ were measured and discussed in relation to the barrier layer depending on the process parameters.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11b
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• pp.34-37
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• 2001

In this study, the capacitance-voltage properties of $(Sr_{1-x}\cdot Ca_x)TiO_3(0.05{\leq}x{\leq}0.20)$-based grain boundary layer ceramics were investigated. The ceramics were fabricated by the conventional mixed oxide method. The sintering temperature and time were $1480\sim1500^{\circ}C$ and 4 hours. respectively. The 2nd phase formed by the thermal diffusion of CuO from the surface leads to very excellent dielectric properties, that is, ${\varepsilon}_r$ >50000, tan$\delta$ <0.05, ${\Delta}C$ < ${\pm}10%.$ The capacitance is almost unchanged below about 20[V] but it decreases slowly about 20[V]. The results of the capacitance-voltage properties indicated that the grain boundary was composed of the continuous insulating layers.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.05b
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• pp.11-14
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• 2004

In this paper, the effect of adhesion properties of semiconductive-insulating interface layer of silicone rubber on electrical properties was investigated. The modifications produced on the silicone surface by oxygen plasma were accessed using ATR-FTIR, contact angle and AFM. Adhesion was obtained from T-peel tests of semiconductive layer having different treatment durations. In addition, ac breakdown test was carried out for elucidating the change of electrical property with duration of plasma treatment. From the results, the treatment in the oxygen plasma produced a noticeable increase in surface energy, which can be mainly ascribed to the the creation of O-H and C=O. It is observed that adhesion performance was determined by not surface energy but roughness level of silicone surface. It is found that ac dielectric strength was increased with improving the adhesion between the semiconductive and insulating interface.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.65 no.8
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• pp.1369-1375
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• 2016

A rapid progress of the next-generation non-volatile memory device has been made in recent years. Metal/insulator/Metal multi-layer structure resistive RAM(ReRAM) has attracted a great deal of attention because it has advantages of simple fabrication, low cost, low power consumption, and low operating voltage. This paper describes the working principle of the ReRAM device, a review of fabrication techniques, and characteristics of flexible ReRAM devices using graphene oxide as an insulating layer and ReRAM devices using multi-layered insulator. The switching characteristics of the above ReRAM devices have been compared. The oxidized graphene could be employed as an insulator of next generation ReRAM devices.

• Journal of the Korean Vacuum Society
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• v.21 no.6
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• pp.354-361
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• 2012

The organic memory device was made by the plasma polymerization method which was not the dry process but the wet process. The memory device consist of the styrene and MMA monomer as the insulating layer, MMA monomer as the tunneling layer and Au thin film as the memory layer which was fabricated by thermal evaporation method. The I-V characteristics of fabricated memory device got the hysteresis voltage of 27 V at 40/-40 V double sweep measuring conditions. At this time, the optimized structure was 7 nm of Au thin film as floating gate, 400 nm of styrene thin film as insulating layer and 30 nm of MMA thin film as tunneling layer. Therefore we got the charge trapping characteristics by the hysteresis voltage. From the paper, styrene indicated a good charge trapping characteristics better than MMA. In the future, we expect to make devices by using styrene thin film rather than Au thin film.

• Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
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• 2003.02a
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• pp.269-271
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• 2003

A typical HTS power transmission cable has multi-layer conductor structure to increase the current capacity. The tapes of the innermost layer are wound on a round former, and adjacent tapes of another layer are separated by a thin insulating film. In steady state, the total current flows in the conductor layer, and consequently there is magnetic field between the inner and outer layer. This paper describes a magnetic field amplitude around the conductor layer and the HTS tape by a transport current. Also, this paper will help for future cable conductor prototypes.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.05a
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• pp.27-31
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• 2001

We fabricated organic electroluminescent(EL) devices with mixed emitting layer of poly(N-vinylcarbazole)(PVK), 2,5-bis(5'-tert-butyl-2-benzoxazoly)thiophene(BBOT), N,N'-diphenyl-N,N'-(3-methyphenyl)-1,1'-biphenyl-4, 4'-diarnine(TPD) and poly(3-hexylthiophene)(P3HT). To improve the external quantum efficiency of EL devices, we added the functional layer to the devices such as LiF insulating layer, carrier confinement layer(BBOT) and hole injection layer(CuPc). In the ITO/emitting layer/Al device, the maximum quantum efficiency at 15V was $1.88{\times}10^{-5}%$. And then, it is increased by a factor of 27 to $5.2{\times}10^{-3}%$ in ITO/CuPc/emitting layer/BBOT/LiF/Al device at 15V.