• Journal of Sensor Science and Technology
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• v.8 no.5
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• pp.421-426
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• 1999

In this paper, we present p-channel GaAs MOSFET having $Al_2O_3$ as gate insulator fabricated on a semi-insulating GaAs substrate, which can be operated in the depletion mode. $1\;{\mu}m$ thick undoped GaAs buffer layer, $4000\;{\AA}$ thick p-type GaAs epi-layer, undoped $500{\AA}$ thick AlAs layer, and $50\;{\AA}$ thick GaAs cap layer were subsequently grown by molecular beam epitaxy(MBE) on (100) oriented semi-insulating GaAs substrate and this wafer was oxidized. AlAs layer was fully oxidized as a $Al_2O_3$ thin film. The I-V, $g_m$, breakdown charateristics of the fabricated GaAs MOSFET showed that wet thermal oxidation of AlAs/GaAs epilayer/S I GaAs was successful in realizing depletion mode p-channel GaAs MOSFET.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.12
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• pp.1063-1066
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• 2009

In this study, we fabricated pentacene organic thin film trasistors(OTFTs) which used aluminum oxide as the gate insulator. Aluminum oxide for OTFTs was deposited on glass substrate with a different deposition rate by E-beam evaporation. In case of the deposition rate of $0.1\;{\AA}$, the fabricated aluminum oxide gate insulating OTFT showed a threshold voltage of -1.36 V, an on/off current ratio of $1.9{\times}10^3$ and field effect mobility $0.023\;cm^2/V_s$.

• Journal of the Korean Applied Science and Technology
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• v.19 no.4
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• pp.335-338
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• 2002

A new process for polymeric gate insulator in field-effect transistors was proposed. Fourier transform infrared absorption spectra were measured in order to identify ODPA-ODA polyimide. Its breakdown field and electrical conductivity were measured. All-organic thin-film transistors with a stacked-inverted top-contact structure were fabricated to demonstrate that thermally evaporated polyimide films could be used as a gate insulator. As a result, the transistor performances with evaporated polyimide was similar with spin-coated polyimide. It seems that the mass-productive in-situ solution-free processes for all-organic thin-film transistors are possible by using the proposed method without vacuum breaking.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.66 no.4
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• pp.721-726
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• 2017

We fabricated stretchable thin-film transistors(TFTs) on a polydimethylsiloxane substrate with patterned polyimide island structures by using an amorphous InGaZnO semiconductor and parylene gate insulator. The TFTs exhibited a field- effect mobility of $5cm^2V^{-1}s^{-1}$ and a current on/off ratio of $10^5$ at a relatively low operating voltage. Furthermore, the fabricated transistors showed no noticeable changes in their electrical performance for large strains of up to 50 %.

• Journal of the Korean Vacuum Society
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• v.21 no.6
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• pp.354-361
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• 2012

The organic memory device was made by the plasma polymerization method which was not the dry process but the wet process. The memory device consist of the styrene and MMA monomer as the insulating layer, MMA monomer as the tunneling layer and Au thin film as the memory layer which was fabricated by thermal evaporation method. The I-V characteristics of fabricated memory device got the hysteresis voltage of 27 V at 40/-40 V double sweep measuring conditions. At this time, the optimized structure was 7 nm of Au thin film as floating gate, 400 nm of styrene thin film as insulating layer and 30 nm of MMA thin film as tunneling layer. Therefore we got the charge trapping characteristics by the hysteresis voltage. From the paper, styrene indicated a good charge trapping characteristics better than MMA. In the future, we expect to make devices by using styrene thin film rather than Au thin film.

• Journal of IKEEE
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• v.23 no.3
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• pp.811-816
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• 2019

The silicon-adsorbed oxygen(Si-O) superlattice grown by ultra high vacuum-chemical vapor deposition(UHV-CVD) was introduced as an epitaxial barrier for silicon quantum electron devices. The current-voltage (I-V) measurement results show the stable and good insulating behavior with high breakdown voltage. It is apparent that the Si-O superlattice can serve as an epitaxially grown insulating layer as possible replacement of silicon-on-insulator(SOI). This thick barrier may be useful as an epitaxial insulating gate for field effect transistors(FETs). The rationale is that it should be possible to fabricate a FET on top of another FET, moving one step closer to the ultimate goal of future silicon-based three-dimensional integrated circuit(3DIC).

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.10a
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• pp.506-508
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• 2005

In general, organic TFTs are comprised of four components: gate electrode, gate dielectric, organic active semiconductor layer, and source and drain contacts. The TFT current, in turn, is typically determined by channel length and width, carrier field effect mobility, gate dielectric thickness and permittivity, contact resistance, and biasing conditions. More recently, a number of techniques and processes have been introduced to the fabrication of OTFT circuits and displays that aim specifically at reduced fabrication cost. These include microcontact printing for the patterning of metals and dielectrics, the use of photochemically patterned insulating and conducting films, and inkjet printing for the selective deposition of contacts and interconnect pattern. In the fabrication of organic TFTs, microcontact printing has been used to pattern gate electrodes, gate dielectrics, and source and drain contacts with sufficient yield to allow the fabrication of transistors. We were fabricated a pentacene OTFTs on flexible PEN film. Au/Cr was used for the gate electrode, parylene-c was deposited as the gate dielectric, and Au/Cr was chosen for the source and drain contacts; were all deposited by ion-beam sputtering and patterned by microcontact printing and lift-off process. Prior to the deposition of the organic active layer, the gate dielectric surface was treated with octadecyltrichlorosilane(OTS) from the vapor phase. To complete the device, pentacene was deposited by thermal evaporation and patterned using a parylene-c layer. The device was shown that the carrier field effect mobility, the threshold voltage, the subthreshold slope, and the on/off current ratio were improved.

• Journal of information and communication convergence engineering
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• v.2 no.2
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• pp.93-96
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• 2004

The a-Si:H TFT using ferroelectric of $SrTiO_3$ as a gate insulator is fabricated on glass. Dielectric characteristics of ferroelectric are superior to $SiO_2$ and $Si_{3}N_{4}$. Ferroelectric increases on-current, decreases threshold voltage of TFT and also improves breakdown characteristics. The a-SiN:H has optical band gap of 2.61 eV, retractive index of 1.8∼2.0 and resistivity of $10^{13}$~$10^{15}$ $\Omega$cm, respectively. Insulating characteristics of ferroelectrics are excellent because dielectric constant of ferroelectric is about 60∼100 and breakdown strength is over 1MV/cm. TFT using ferroelectric has channel length of 8∼20 $\mu\textrm{m}$ and channel width of 80∼200 $\mu\textrm{m}$. And it shows that drain current is 3.4$\mu\textrm{A}$ at 20 gate voltage, $I_{on}$/$I_{off}$ is a ratio of $10^5$~$10^8$ and $V_{th}$ is 4∼5 volts, respectively. In the case of TFT without ferroelectric, it indicates that the drain current is 1.5 $\mu\textrm{A}$ at 20 gate voltage and $V_{th}$ is 5∼6 volts. With the improvement of the ferroelectric thin film properties, the performance of TFT using this ferroelectric has advanced as a gate insulator fabrication technology is realized.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.181-184
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• 1999

This paper presents the accurate deembeding method for pad and parasitics of MOSFET device. rad effects are deembedded using THRU LINE, which is much simpler method without laborious fitting procedure compared with conventional OPEN and SHORT pad modeling. Parasitic resistance extraction uses the algebraic relation between increments of inversion layer charge and oxide capacitance. It is especially adequate for insulating gate junction device. Extracted parasitics are verified through comparing modeled and measured S parameters.

• 한국정보디스플레이학회:학술대회논문집
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• 2000.01a
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• pp.215-216
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• 2000

We fabricated the thin-film transistors using organic semiconductor, pentacene, on $SiN_x$, gate insulator. X-ray diffraction experiments were performed for the sample after heat-treatments at higher temperatures. We confirmed that we obtained "thin-film phase" from the condition used here. From the electrical measurements, we also confirmed that no charges are accumulated at the interface between organic and insulating layer, and FET characteristics of the organic FET using pentacene was discussed.