• Journal of Korea Society of Digital Industry and Information Management
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• v.11 no.3
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• pp.31-43
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• 2015

In this paper, we discuss a code generation technique for custom transport triggered architecture (TTA) from a high-level language structure. This methodology is implemented by using TTA-based Co-design Environment (TCE) tool. The results show how the scheduler exploits instruction level parallelism in the custom target architecture and source program. Thus, the scheduler generates parallel TTA instructions using lower cycle counts than the sequential scheduling algorithm. Moreover, we take Tensilica tool to make a comparison with TCE. Because of the efficiency of TTA, TCE takes less execution cycles compared to Tensilica configurations. Finally, this paper shows that it requires only 7 cycles to generate the parallel TTA instruction set for implementing Cyclic Redundancy Check (CRC) applications as an input design, and presents the code generation technique to move complexity from the processor software to hardware architecture. This method can be applicable lots of channel Codecs like CRC and source Codecs like High Efficiency Video Coding (HEVC).

• The Transactions of the Korea Information Processing Society
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• v.4 no.6
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• pp.1481-1494
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• 1997

In hard real-time systems, a timing fault may yield catastrophic results. Dynamic scheduling provides the flexibility to compensate for unexpected events at runtime; however, scheduling overhead at runtime is relatively large, constraining both the accuracy of the timing and the complexity of the scheduling analysis. In contrast, static scheduling need not have any runtime overhead. Thus, it has the potential to guarantee the precise time at which each instruction implementing a control action will execute. This paper presents a new approach to the problem of analyzing high-level language code, augmented by arbitrary before and after timing constraints, to provide a valid static schedule. Our technique is based on instruction-level complier code scheduling and timing analysis, and can ensure the timing of control operations to within a single instruction clock cycle. Because the search space for a valid static schedule is very large, a novel adaptive genetic search algorithm was developed.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.6B
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• pp.544-552
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• 2003

This paper suggests an instruction code sufficiency algorithm preventing data collision when multiple transponders attempt to connect in the radio frequency identification system. Conventional time domain procedure generates unconditional collision. On the other hand, this algorithm prevents data collision by transmitting data when it meets instruction code. When multiple transponders are transmitting data coincidently, they exploit desired data with using difference of arrival time generated by recognition distance, respectively. As a result of simulation, utilizing the wireless recognition system, adopting the suggested algorithm, operating in 13.56MHz frequency band, it verify that there is Anti-collision and data loss by ensuring transmission time difference of one bit by adopting this algorithm.

• The Journal of Korean Association of Computer Education
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• v.7 no.6
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• pp.27-35
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• 2004

Data structure and algorithm are primary courses for computer programming instruction. However, now those are not interesting courses for students because the programming instruction methodologies that used these courses are not the proper methodologies for the visual and windows programming. The Sorting programming is the same as other data structures. Therefore, we developed the VTSPI (Visualization Tool for Sorting Programming Instruction) which is a software component to instruct sorting program effectively for solving these problems. As a result, students can code, understand and debug their programs because VTPSI is software components based on visual programming.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.8
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• pp.1221-1230
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• 1990

This paper presents a code generation method and an effective handling algorithm of ingeger constant multiplication for RISC machines in compiler design. As RISC Architectures usually use faster and more simply formed instructions than CISC's and most RISC processors do not have an integer multiplication instruction, it is required an effective algorithm to process integer multiplication. For the proposed code generator, Portable C Compiler(PCC) is redesigned to be suitable for an RISC machine, and composed an addition chain is built up to allow fast execution of constant multiplication, a part of integer one whicch appears very frequency in code generation phase.

• The Transactions of the Korea Information Processing Society
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• v.7 no.2
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• pp.520-528
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• 2000

he speed of microprocessor getting faster, the data transfer width between the microprocessor and the memory becomes a critical part to limit the system performance. So the study of the computer architecture with the high code density is cmerged. In this paper, a tentative Bi-Length Instruction Set Computer(BISC) that consists of 16 bit and 32 bit length instructions is proposed as the high code density 32 bit microprocessor architecture. The 32 bit BISC has 16 general purpose registers and two kinds of instructions due to the length of offset and the size of immediate operand. The proposed 32 bit BISC is implemented by FPGA, and all of its functions are tested and verified at 1.8432MHz. And the cross assembler, the cross C/C++ compiler and the instruction simulator of the 32 bit BISC are designed and verified. This paper also proves that the code density of 32 bit BISC is much higher than the one of traditional architecture, it accounts for 130~220% of RISC and 130~140% of CISC. As a consequence, the BISC is suitable for the next generation computer architecture because it needs less data transfer width. And its small memory requirement offers that it could be useful for the embedded microprocessor.

• KIPS Transactions on Computer and Communication Systems
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• v.2 no.3
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• pp.111-116
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• 2013

With technology scaling, soft error rate has greatly increased in embedded systems. Due to high performance and low power consumption, VLIW (Very Long Instruction Word) architectures have been widely used in embedded systems and thus many researches have been studied to improve the reliability of a system by duplicating instructions in VLIW architectures. However, existing studies have ignored the feature, called VLES (Variable Length Execution Set), which is adopted in most modern VLIW architectures to reduce code size. In this paper, we propose how to support instruction duplication in VLIW architecture with VLES. Our experimental results demonstrate that a VLIW architecture with VLES shows 64% code size decrement on average at the cost of about 4% additional cell area as compared to the case of a VLIW architecture without VLES when instruction duplication is applied to both architectures. Also, it is shown that the case with VLES does not cause extra execution time compared to the case without VLES.

• Journal of The Korean Association For Science Education
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• v.29 no.1
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• pp.116-136
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• 2009

Since there are differences in the content, structure and functions of interpersonal communication during the practice of school science classes, it needs to articulate the difference of the modality of pedagogical practice in order to understand science teaching in detail. These characteristics of science teaching can be investigated by further insightful analysis on language in the science classroom. In this study, classroom discourse language codes using Bernstein's code theory were analyzed in the case of a middle school science class on the unit of minerals. The discourse language code was identified by the value of classification, which revealed power relations to the contexts of discourse and participants of discourse. It was also identified by the value of framing, which showed hierarchical relation between teacher and students as discourse subjects, and discursive control on the initiative of discourse. The results addressed that six types of discourse language codes were constructed and that those language codes reflected diverse modalities of science teaching from student-centered instruction to teacher-centered instruction in relation to classroom discourse. The modality of science teaching according to the transition tendencies of discourse language code showed dynamic variations of 'controlled student-centeredness inducing teaching' - 'positional student-centeredness permissive teaching' - 'controlled students' participation permissive teaching' - 'controlled student-centeredness facilitative teaching' - 'student-centeredness enhancing teaching'. In addition, results released that discursively and hierarchically weak control of discourse is necessary for enhancing student-centeredness of science teaching. Moreover, teaching practice enhancing student-centeredness can be accomplished by the harmony of a teacher's perception of discourse language code and his/her orientation to constructivist teaching and student-centered teaching.

• Journal of the Korean Professional Engineers Association
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• v.33 no.4
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• pp.53-58
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• 2000

Within 10years, it will be possible to integrate 10B transistors on a single chip microprocessor which wilt operate far beyond GHZ, and it will execute about 20-200 instructions per clock cycle from widely variable instruction streams leveraging SMT(Simultaneous Multithreading) technology . Also it will decouple the current legacy X86 binary compatibility by translation layer such as code morphing technology.

• Journal of KIISE:Software and Applications
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• v.37 no.11
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• pp.851-858
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• 2010

Most mobile devices use a NAND flash memory as their secondary memory. A compressed code of the firmware is stored in the NAND flash memory of mobile devices in order to reduce the size and the loading time of the firmware from the NAND flash memory to a main memory. In order to use a demand paging properly, a compressed code should be decompressed very quickly. The thesis introduces a new dictionary based compression algorithm for the fast decompression. The introduced compression algorithm uses a different method with the current LZ method by storing the "exclusive or" value of the two instructions when the instruction for compression is not equal to the referenced instruction. Therefore, the thesis introduces a new compression format that minimizes the bit operation in order to improve the speed of decompression. The experimental results show that the decoding time is reduced up to 5 times and the compression ratio is improved up to 4% compared to the zlib. Moreover, the proposed compression method with the fast decoding time leads to 10-20% speed up of booting time compared to the booting time of the uncompressed method.