• 대한전기학회:학술대회논문집
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• 대한전기학회 1994년도 하계학술대회 논문집 A
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• pp.495-497
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• 1994

Given the constraint of the AC input power factor and the DC-link voltage and current ripple in voltage source inverter, minimizing the size and cost of the DC-link fitter components is very important. This paper presents a procedure for the selection of DC-link filler element values in a three-phase PWM voltage source inverter-fed induction motor drive system, which can not only satisfy the requirements for the system performance but also minimize the filter size.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2011년도 전력전자학술대회
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• pp.25-26
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• 2011

In some cases of grid connected system using photovoltaic modules, high voltage step up ratio is required. In this paper, non-isolated 2-stage cascaded boost converter with coupled inductor is proposed. Due to reduce the input current ripple and size of the inductor by using coupled inductor method, this topology is suitable for MIC(Module Integrated Converter). The operational characteristic of the proposed topology is verified through the theorical analysis, simulation and experimental waveform.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2004년도 전력전자학술대회 논문집(1)
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• pp.308-311
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• 2004

A novel single-stage power factor corrected (PFC) drive for switched reluctance motor (SRM) is presented to achieve sinusoidal, near unity power factor input current. The proposed PFC SRM drive has no additional active switch. And a single-stage approach, which combines a DC link capacitor used as do source and a drive used for driving the motor into one power stage, has a simple structure and low cost. The characteristics and validity of the proposed circuit will be discussed in depth through the experimental results.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2012년도 추계학술대회 논문집
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• pp.81-82
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• 2012

본 논문은 고효율 획득 및 입력전류 리플 저감을 위한 3상 부스트 컨버터의 동작 알고리즘을 제안한다. 입력전압별로 인덕터 전류에 따른 투자율 감소를 고려하여 DCM 및 BCM 동작시의 효율과 입력 전류 리플을 수식적으로 분석한다. 이에 따라 3상 부스트 컨버터를 경계 도통 모드+불연속 도통 모드의 혼합 모드에서 동작시키고 타당성을 실험을 통해 검증한다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.537-538
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• 2008

A step-down DC-DC converter with On-chip Compensation for battery-operated portable electronic devices which are designed in 0.18um CMOS standard process. In an effort to improve low load efficiency, this paper proposes the PFM (Pulse Frequency modulation) voltage mode 1MHz switching frequency step-down DC-DC converter with on-chip compensation. Capacitor multiplier method can minimize error amplifier compensation block size by 20%. It allows the compensation block of DC-DC converter be easily integrated on a chip and occupy less layout area. But capacitor multiplier operation reduces DC-DC converter efficiency. As a result, this converter shows maximum efficiency over 87% for the output voltage of 1.8V (input voltage : 3.3V), maximum load current 500mA, and 0.14% output ripple voltage. The total core chip area is $mm^2$.

• IEIE Transactions on Smart Processing and Computing
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• 제3권6호
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• pp.425-429
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• 2014

This paper proposes a DC-DC Buck-Converter with DT-CMOS (Dynamic Threshold-voltage MOSFET) Switch. The proposed circuit was evaluated and compared with a CMOS switch by both the circuit and device simulations. The DT-CMOS switch reduced the output ripple and the conduction loss through a low on-resistance. Overall, the proposed circuit showed excellent performance efficiency compared to the converter with conventional CMOS switch. The proposed circuit has switching frequency of 1.2MHz, 3.3V input voltage, 2.5V output voltage, and maximum current of 100mA. In addition, this paper proposes a SCP (Short Circuit Protection) circuit to ensure reliability.

• Journal of Power Electronics
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• 제16권2호
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• pp.447-454
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• 2016

A single-ended primary-inductor converter (SEPIC) features low input current ripple and output voltage up/down capability. However, the switching devices in a two-level SEPIC suffer from high voltage stresses and switching losses. To cope with this drawback, this study proposes a three-level SEPIC that uses a low voltage-rated switch and thus achieves better switching performance compared with the two-level SEPIC. The three-level SEPIC can reduce switch voltage stresses and switching losses. The converter operation and control method are described in this work. The experimental results for a 500 W prototype converter are also discussed. Experimental results show that unlike the two-level SEPIC, the three-level SEPIC achieves improved power efficiency with balanced capacitor voltages.

• Journal of Power Electronics
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• 제18권3호
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• pp.651-661
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• 2018

This paper suggests a new non-isolated high voltage gain DC-DC converter with two switches. The proposed two-switch converter has the following characteristics: a high voltage gain, a continuous input current with a small ripple, a reduction in the size of the inductor, and a simple circuit with only a few elements. A theoretical analysis, guidelines for parameter selection, and a comparison with conventional non-isolated high step-up converters are presented. A prototype of 250 W is set up to demonstrate the correctness of the proposed converter. Results obtained from simulations and experiments are presented.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2018년도 전력전자학술대회
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• pp.428-429
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• 2018

본 논문은 결합 인덕터를 이용한 입력 전류 리플이 없는 고승압 캐스케이드 부스트 DC-DC 컨버터를 제안한다. 기존 캐스케이드 부스트 컨버터의 단점을 보완하기 위해 제안되었다. 제안된 컨버터는 1차 부스트 단의 보조회로에 의해 입력 전류 리플이 상당히 제거되었으며 2차 부스트 단에 결합 인덕터를 적용하여 높은 전압 이득을 달성하였다. 제안된 컨버터는 이론적 해석과 200[V]-200[W]하드웨어 시작품을 제작하여 검증하였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 춘계학술대회 논문집 전기기기 및 에너지변환시스템부문
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• pp.164-167
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• 2005

This paper present ZVS Half-Bridge converter Using IM(Integrated Magnetics). In converter system, magnetic components are important devices used for energy storage, energy transfer, galvanic isolation and filtering. The purposes of IM(Integrated Magnetics) are to reduce the number of magnetic components and voltage/current ripple. This topology is use of three magnetics components thus increasing the cost and size of the system. A prototype featuring 300V input, 15V output, 400kHz switching frequency, and 150W output power.