• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.6 s.360
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• pp.8-18
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• 2007

In this paper, a 4bit cell way structure of PoRAM and the sensing method to drive this structure are researched. PoRAM has a different operation from existing SRAM and DRAM. The operation is that when certain voltage is applied between top electrode and bottom electrode of PoRAM device we can classify the cell state by measuring cell current which is made by changing resistance of the cell. In the decoder selected by new-addressing method in the cell array, the row decoder is selected "High" and the column decoder is selected "Low" then certain current will flow to the bit-line. Because this current is detect, in order to make large enough current, the voltage sense amplifier is used. In this case, usually, 1-stage differential amplifier using current mirror is used. Furthermore, the detected value at the cell is current, so a diode connected NMOSFET, that is, a device resistor is used at the input port of the differential amplifier to converter current into voltage. Using this differential amplifier, we can classify the cell states, erase mode is "Low" and write mode is "High", by comparing the input value, Vin, that is a product of current value multiplied by resistor value with a reference voltage, Vref.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.1
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• pp.29-36
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• 2009

In this paper, the design and implementation of LNA and down-mixer using 90 nm CMOS process are presented for 60 GHz band WPAN receiver. In order to extract characteristics of the transistor used to design each elements under the optimum bias conditions, the S-parameter of the manufactured cascode topology was measured and the effect of the RF pad was removed. Measured results of 3-stages cascode type LNA the gain of 25 dB and noise figure of 7 dB. Balanced type down-mixer with a balun at LO input port shows the conversion gain of 12.5 dB within IF frequency($8.5{\sim}11.5\;GHz$) and input PldB of -7 dBm. The size and power consumption of LNA and down-mixer are $0.8{\times}0.6\;mm^2$, 43 mW and $0.85{\times}0.85\;mm^2$, 1.2 mW, respectively.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.7
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• pp.771-777
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• 2008

In this paper, a frequency doubler using modified time-delay technique is proposed. A voltage controlled delay line (VCDL) in the proposed frequency doubler compensates the group delay time mismatching between input and delayed signal. With the group delay time matching and waveform shaping using the adjustable Schmitt triggers, the unwanted fundamental component($f_0$) and the higher order harmonics such as third and fourth are diminished excellently. In result, only the doubled frequency component($2f_0$) appears dominantly at the output port. The frequency doubler is designed at 1.15 GHz of $f_0$ and fabricated with TSMC $0.18\;{\mu}m$ CMOS process. The measured output power at $2f_0$ is 2.67 dBm when the input power is 0 dBm. The obtained suppression ratio of $f_0,\;3f_0$, and $4f_0$ to $2f_0$ are 43.65, 38.65 and 35.59 dB, respectively.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.12A
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• pp.1922-1931
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• 1999

A multicast traffic’s feature is the function of providing a point to multipoints cell transmission, which is emerging from the main function of ATM switch. However, when a conventional point-to-point switch executes a multicast function, the excess load is occurred because unicast cell as well as multicast cell passed the copy network. Additionally, due to the excess load, multicast cells collide with other cells in a switch. Thus a deadlock that losses cells raises, extremely diminishes the performance of switch. An input queued switch also has a defect of the HOL (Head of Line) blocking that less lessens the performance of the switch. In the proposed multicast switch, we use shared memory switch to reduce HOL blocking and deadlock. In order to decrease switch’s complexity and cell's processing time, to improve a throughput, we utilize the method that routes a cell on a separated paths by traffic pattern and the scheduling algorithm that processes a maximum 2N cell at once in the control part. Besides, when cells is congested at an output port, a cell loss probability increases. Thus we use the Output Memory (OM) to reduce the cell loss probability. And we make use of the method that stores the assigned memory (UM, MM) with a cell by a traffic pattern and clears the cell of the Output memory after a fixed saving time to improve the memory utilization rate. The performance of the proposed switch is executed and compared with the conventional policy under the burst traffic condition through both the analysis based on Markov chain and simulation.

• The Journal of the Acoustical Society of Korea
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• v.14 no.2E
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• pp.91-97
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• 1995

This paper describes the implementation of a multi-channel audio codec for HETV. This codec has the features of the 3/2-stereo plus low frequency enhancement, downward compatibility with the smaller number of channels, backward compatibility with the existing 2/0-stereo system(MPEG-1 audio), and multilingual capability. The encoder of this codec consists of 6-channel analog audio input part with the sampling rate of 48 kHz, 4-channel digital audio input part and three TMS320C40 /DSPs. The encoder implements multi-channel audio compression using a human perceptual psychoacoustic model, and has the bit rate reduction to 384 kbit/s without impairment of subjective quality. The decoder consists of 6-channel analog audio output part, 4-channel digital audio output part, and two TMS320C40 DSPs for a decoding procedure. The decoder analyzes the bit stream received with bit rate of 384 kbit/s from the encoder and reproduces the multi-channel audio signals for analog and digital outputs. The multi-processing of this audio codec using multiple DSPs is ensured by high speed transfer of date between DSPs through coordinating communication port activities with DMA coprocessors. Finally, some technical considerations are suggested to realize the problem of real-time operation, which are found out through the implementation of this codec using the MPEG-2 layer II sudio coding algorithm and the use of the hardware architecture with commercial multiple DSPs.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.5
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• pp.413-420
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• 2009

We propose a novel feed network for a $2{\times}2$ array antenna to form a sectoral conical beam. The proposed feed network, which is a symmetrical structure, consists of four $90^{\circ}$ hybrids, a crossover, and four $90^{\circ}$ delay lines. To verify the performance of the feed network a $2{\times}2$ array antenna and the feed network are fabricated on a microstrip structure, and the radiation patterns are measured at the center frequency of 2.57 GHz. The maximum radiation is measured at the $45^{\circ}$ elevation angle and at the $45^{\circ}$, $135^{\circ}$, $225^{\circ}$, and $315^{\circ}$ azimuth angles depending on the choice of the input port of the feed network.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.39 no.3
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• pp.65-70
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• 2002

This paper discusses the work-in-progress of a system to control a moving robot over the WWW(World Wide Web). That is, we describes the experimental results and control methods of system over the world wide web. The remote control of the system is controlled by accessing a simple form of interface that is connected to the server. For this application, a remote operator should have a general-purpose computer with Internet connection and a WWW browser to remotely operate the line-tracer through the Internet. As a remote operator summits an input by operating html files in the server, the program written in java is operated the equipment is being connected to the serial port. By being transmitted to the line-tracer through the infra-red sensor, the remote controlled signal is operated in distance. As a tool in order to identify the system's operation of the over the web is used the line-tracer. 

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.45 no.2
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• pp.41-47
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• 2008

Most of media compression CODECs adopts the variable length coding method. This paper proposes special registers and instruction set for bit stream process in order to accelerate the decoding process of the variable length code. The instruction set shares the conventional data path to minimize additional costs. And bit stream is read from the memory instead of the special port. Therefore the instruction set minimizes the change of the processor, and is adopted without any additional input controller and buffer, and accelerate decoding process of variable length code. The data path of the instruction set needs additional 65 bits memory and 344 equivalent gates, 0.19 ns delay under TSMC $0.25{\mu}m$ technology. The instruction set reduced the execution time of the variable length code decoding process in H.264/AVC by about 55%.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.11
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• pp.1271-1278
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• 2007

A novel frequency multiplier using composite right/left-handed transmission line is proposed. The left-handed transmission line in the proposed frequency multiplier suppresses the fundamental component($f_0$), while the composite right/left-handed ${\lambda}/4$ open stub diminishes unwanted harmonics. Due to the combination of the left-handed transmission line and composite right/left-handed ${\lambda}/4$ open stub, the only desirable multiplied frequency component such as 3 $f_0$ and 4 $f_0$ are obtained at the output port excellently. For the example of the proposed design, frequency multipliers are designed at 1 GHz of $f_0$ and measured. The measured output power of 3 $f_0$ and 4 $f_0$ is -5.67 dBm and -6.43 dBm, respectively, when the fundamental input power was 0 dBm.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.3 no.2
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• pp.281-290
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• 1999

This paper presents the development of a high power amplifier for a transmitter of INMARSAT-C operating at L-band(1626.5∼1646.5 MHz). To simplify the fabrication process, the whole system is designed of two parts composed of a driving amplifier and a high power amplifier The HP's AT-41486 is used for driving part and the SGS-THOMSON microelectronics' STM1645 is used the high power amplifier. The SSPA(Solid State Power Amplifier) was fabricated by the both circuits of RF and temperature compensation in aluminum housing. The realized SSPA has more than 36 dB for small signal within 20MHz bandwidth, and the voltage standing wave ratios(VSWR) of input and output Port are less than 1.5:1, respectively. The output Power of 42.2 dBm is achieved at the 1636.5 MHz. These results reveal a high power amplifier of 20 Watt which is the design target.