• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.117-120
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• 1999

Input queueing is useful for high bandwidth switches and routers because of lower complexity and fewer circuits than output queueing. The input queueing switch, however, suffers HOL-Blocking, which limits the throughput to 58%. To get around this low throughput, we propose a simple scheduling algorithm called Synchronous Input Port (SIP). This method synchronize packets and switching without blocking, which is shown to have better performance over the established algorithms

• ETRI Journal
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• 제28권3호
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• pp.355-363
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• 2006

This paper presents a low-cost RF parameter estimation technique using a new RF built-in self-test (BIST) circuit and efficient DC measurement for 4.5 to 5.5 GHz low noise amplifiers (LNAs). The BIST circuit measures gain, noise figure, input impedance, and input return loss for an LNA. The BIST circuit is designed using $0.18\;{\mu}m$ SiGe technology. The test technique utilizes input impedance matching and output DC voltage measurements. The technique is simple and inexpensive.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(1)
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• pp.145-148
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• 2002

This paper has been studied a predistorter which is able to linierizing of RF amplifier using schottkey. If input signal level is low, input signal is delivered directly. And if input signal level is high, input signal Is delivered with decreasing. So RF amplifier always works at saturation region .When this predistorter is used to simplified C-class RF amplifier, we have concluded that efficiency is improved about 3%.

• 인터넷정보학회논문지
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• 제6권5호
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• pp.73-83
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• 2005

본 논문에서는 착용형 컴퓨터를 위한 촉각 사용자 인터페이스 및 이를 활용한 개선된 입력알고리즘을 제안한다. 유비쿼터스 환경의 도래에 따른 차세대 PC의 진화 방향은, 인간이 느끼는 색상, 빛의 밝기, 소리, 향기, 맛, 감촉 등의 오감정보의 효과적인 융합과 재현을 목표로, 사용자 중심의 인간-기계 관계의 형성으로 나아가고 있다. 그러나 이러한 기능의 다양함과는 별개로, H/W플랫폼의 진화 방향은 항상 휴대가 간편하도록 소형화, 경량화 및 착용화 형태로 개발되어지고 있다. 이러한 차세대 PC의 소형화 및 경량화 관련 진화에 가장 큰 걸림돌이 되는 부분은 사용자 입출력 장치로서, 기존의 키보드 및 모니터 등의 장치를 활용한 사용자 인터페이스에는 소형화의 한계가 존재하고 있는 실정이다. 본 논문에서는 이러한 소형화, 경량화 및 착용화를 위한 새로운 방법의 사용자 입력장치 및 입력알고리즘을 제안한다. 또한 기존에 제안되어진 유사 장치와의 비교 분석을 통한 제안시스템 및 알고리즘의 실효성을 평가한다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 V
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• pp.2843-2846
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• 2003

This paper proposes a PWM(Pulse Width Modulation) circuit using CMOS OTA with a single-voltage supply. The OTA employed has an input stage which consists of a pair of two MOSFETs operating in plural operation regions. The MOSFETs work complemetarily and realize a rail-to-rail input range. The input stage requires no matching of an n-channel type input circuit and a p-channel type input circuit unlike conventional rail-to-rail input stages because the input stage is realized by single channel type MOSFETs. In order to confirm the validity of the proposed circuit, it is simulated by H-SPICE program. Futhermore, the proposed circuit will be integrated on chip using 0.35 $\mu\textrm{m}$ CMOS technology.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 추계학술대회 논문집 전기기기 및 에너지변환시스템부문
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• pp.259-261
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• 2003

Generally, there is an input capacitor in front of PV(Photovoltaic) inverter in DG(Distributed Generation). This input capacitor mainly works in order to stabilize the PV output voltage. However, input capacitors, which are being used in domestic market are not well known about their appropriate value and also there is no information for selecting the suitable value of input capacitor. Therefore, the author suggests that the stand-alone PV inverter is considered to analyse appropriate value of input capacitor and then recommends the appropriate value of input capacitor through simulation.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권6호
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• pp.706-711
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• 2014

A low power 6-bit flash ADC that uses an input voltage range detection algorithm is described. An input voltage level detector circuit has been designed to overcome the disadvantages of the flash ADC which consume most of the dynamic power dissipation due to comparators array. In this work, four digital input voltage range detectors are employed and each input voltage range detector generates the specific clock signal only if the input voltage falls between two adjacent reference voltages applied to the detector. The specific clock signal generated by the detector is applied to turn the corresponding latched comparators on and the rest of the comparators off. This ADC consumes 68.82 mW with a single power supply of 1.2V and achieves 4.3 effective number of bits for input frequency up to 1 MHz at 500 MS/s. Therefore it results in 4.6 pJ/step of Figure of Merit (FoM). The chip is fabricated in 0.13-um CMOS process.

• 전자공학회논문지S
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• 제35S권4호
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• pp.58-66
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• 1998

In many situations, it is very important to identify a certain unkown system, it from its input-output data. For this purpose, several system modeling algorithms have been suggested heretofore, and studies regarding the fuzzy modeling based on its nonlinearity get underway as well. Generatlly, fuzzy models have the capability of dividing input space into several subspaces, compared to linear ones. But hitherto subggested fuzzy modeling algorithms do not take into consideration the correlations between components of sample input data and address them independently of each other, which results in ineffective partition of input space. Therefore, to solve this problem, this letter proposes a new fuzzy modeling algorithm which partitions the input space more efficiently that conventional methods by taking into consideration correlations between components of sample data. As a way to use correlation and divide the input space, the method of principal component is ued. Finally, the results of computer simulation are given to demonstrate the validity of this algorithm.

• Journal of Power Electronics
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• 제16권6호
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• pp.2024-2034
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• 2016

This paper presents a DC-DC buck converter with a Phase-Locked Loop (PLL) that can compensates for power efficiency degradation over a wide input range. Its switching frequency is kept at 2 MHz and the delay difference between the High side driver and the Low side driver can be minimized with respect to Process, Voltage and Temperature (PVT) variations by adopting the PLL. The operation mode of the proposed DC-DC buck converter is automatically changed to Pulse Width Modulation (PWM) or PWM frequency modes according to the load condition (heavy load or light load) while supporting a maximum load current of up to 1.2 A. The PWM frequency mode is used to extend the CCM region under the light load condition for the PWM operation. As a result, high efficiency can be achieved under the light load condition by the PWM frequency mode and the delay compensation with the PLL. The proposed DC-DC buck converter is fabricated with a $0.18{\mu}m$ BCD process, and the die area is $3.96mm^2$. It is implemented to have over a 90 % efficiency at an output voltage of 5 V when the input range is between 8 V and 20 V. As a result, the variation in the power efficiency is less than 1 % and the maximum efficiency of the proposed DC-DC buck converter with the PLL is 95.4 %.

• 한국컴퓨터정보학회논문지
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• 제11권5호
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• pp.59-67
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• 2006

본 논문에서는 지수평활을 이용한 법원경매 정보 시스템의 낙찰가 예측 방법을 제안하였다. 이 시스템은 권리분석을 위하여 낙찰가를 예측하고, 낙찰예측가에 따라 배당 정보를 제공하도록 설계되어 있으며 이를 구현하기 위하여 물건 자료의 입력 인터페이스와 정보 제공을 위한 웹 인터페이스를 구축하였다. 자료 입력 인터페이스는 자료의 입력, 수정, 삭제 기능을 가지며, 웹 인터페이스는 법원경매 물건을 중심으로 관련 정보를 제공한다. 실시간 정보 제공에 초점을 두고 자동 권리분석이 가능하도록 하기 위하여 낙찰가를 시계열 자료로 표현하여 지수평활을 이용한 낙찰예상가를 예측하는 방법을 제안하고, 기존의 방법과 비교 실험을 통하여 제안방법의 유효성을 검증한다.