• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.114-117
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• 1999

Hluchyj and Karlo proposed to simple algorithm for input buffer queue service in packet switch. This paper using not multiple queue but single queue shows, in first, the improved processing rate. Next shows a few fairness as accessing, Finally shows more improved than the existed method.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.122-125
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• 1999

In this paper, we propose a new architecture of the Banyan switch for a high speed networking and the high speed parallel computer. The proposed switching network with a remodeled architecture is a newly modified Banyan network with eight input and output pots, respectively. We have analysed the maximum throughput of the revised switch. Our analyses has shown that under the uniform random traffic load, the FIFO discipline is limited to 70％. Therefore the result of the analyses shows that the results of the networking simulation with the new switch are feasible and if we adopt such as new architecture of the revised model of the Banyan switch, the hardware complexity can be reduced. The FIFO discipline has increased about 11% when we compare the switching system with the input buffer system. We have designed and verified the new switching system in VHDL.

• Proceedings of the KIEE Conference
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• 1990.07a
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• pp.525-528
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• 1990

In this paper, a CMOS Operational Transconductance Amplifier (OTA) which is used for high-frequency operation has been designed and simulated by SPICE 2G program. To increase input linear range, the input stage is designed by cross-coupled pair. And the output stage insert buffer stage for the buffing and gain. The band-width of designed OTA is $50{\sim}60$ [MHz].

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.537-540
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• 2000

In this paper, we propose and design new architecture of the modified Banyan switch for a high speed networking and the high speed parallel computer. The proposed switching network with a remodeled architecture is a newly modified Banyan network with eight input and output ports. The switch scheme is that two packets may arrive on different inputs destined for the same output. We have analyzed the maximum throughput of the revised switch. The result of the analyses shows good agreement simulation and if we adopt such architecture of the revised model of the Banyan switch, the hardware complexity can be reduced. The FIFO discipline has increased about lloio when we compare the switching system with the input buffer system. We have designed and verified the switching system in VHDL.

• Journal of Korean Institute of Industrial Engineers
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• v.22 no.3
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• pp.313-324
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• 1996

A new policy to determine the waiting position of an idle Automated Guided Vehicle(AGV) is proposed and its performance is compared with the existing waiting position policies. Unlike the existing policies, the queue length in the input buffer is considered in the new policy. As a result, the waiting position based on the new policy depends on the status of the system. The simulation result indicates that the proposed policy reduces the waiting time in both the input and the output buffers significantly, regardless of the number of AGVs in the system. Therefore, the manufacturing lead time can be minimized.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.4
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• pp.691-698
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• 2003

We extend the sue of the method of least square to develop a recursive algorithm for the design of adaptive transversal filters such that, given the least-square estimate of this vector of the filter at iteration n-l, we may compute the updated estimate of this vector at iteration n upon the arrival of new data. We begin the development of the RLS algorithm by reviewing some basic relations that pertain to the method of least squares. Then, by exploiting a relation in matrix algebra known as the matrix inversion lemma, we develop the RLS algorithm. An important feature of the RLS algorithm is that it utilizes information contained in the input data, extending back to the instant of time when the algorithm is initiated. In this paper, we propose new tap weight updated RLS algorithm in adaptive transversal filter with data-recycling buffer structure. We prove that convergence speed of learning curve of RLS algorithm with data-recycling buffer is faster than it of exiting RLS algorithm to mean square error versus iteration number. Also the resulting rate of convergence is typically an order of magnitude faster than the simple LMS algorithm. We show that the number of desired sample is portion to increase to converge the specified value from the three dimension simulation result of mean square error according to the degree of channel amplitude distortion and data-recycle buffer number. This improvement of convergence character in performance, is achieved at the B times of convergence speed of mean square error increase in data recycle buffer number with new proposed RLS algorithm.

• Journal of IKEEE
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• v.13 no.1
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• pp.19-29
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• 2009

For two input ESD protection schemes utilizing the NMOS protection device or the lvtr_thyristor protection device, which is suitable for high-frequency CMOS ICs, we attempt an in-depth comparison study on the HBM ESD protection level in terms of lattice heating inside the protection devices and the peak voltage applied to the gate oxides in the input buffer through DC, mixed-mode transient, and AC analyses utilizing the 2-dimensional device simulator. For this purpose, we suggest a method for the equivalent circuit modeling of the input HBM test environment for the CMOS chip equipped with the input ESD protection circuit. And by executing mixed-mode simulations including up to four protection devices and analyzing the results for five different test modes, we attempt a detailed analysis on the problems which can be occurred in a real HBM test. In this procedure, we explain about the strength and weakness of the two protection schemes as an input protection circuit for high-frequency ICs, and suggest guidelines relating to the design of the protection devices.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.2 no.4
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• pp.583-592
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• 1998

In this paper, the cell loss rate is analyzed in terms of the input traffic stream of different speed in ATM network. The cell loss rate is calculated by birth-death process of Leaky-Bucket mechanism as the representative algorithm of usage parameter control. The cell loss rate assumed 2-state MMPP input process to be birth-death process by considering the character of token pool about finite capacity queue. The results from numerical analysis show that the cell loss rate decreases abruptly according to the buffer size increase. The computer simulation by SIMSCRIPT II.5 has been done and compared with on/off input source case to verify the analysis results.

• Progress in Superconductivity and Cryogenics
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• v.15 no.3
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• pp.35-39
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• 2013

In this paper, we present test results of developed 100 W class linear compressor for Stirling-type pulse tube refrigerator. The fabricated linear compressor has dual-opposed configuration, free piston and moving magnet type linear motor. Power transfer, efficiency and required pressure waveform are predicted with designed and measured specifications. In experiments, room temperature test with flow impedance is conducted to evaluate performance of developed linear compressor. Flow impedance is loaded to compressor with metering valve for flow resistance, inertance tube for flow inertance and buffer volumes for flow compliance. Several operating parameters such as input voltage, current, piston displacement and pressure wave are measured for various operating frequency and fixed input current level. Behaviors of dynamics and performance of linear compressor as varying flow impedance are discussed with measured experimental results. The developed linear compressor shows 124 W of input power, 86 % of motor efficiency and 60 % of compressor efficiency at its resonant operating condition.

• Journal of Internet Computing and Services
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• v.9 no.2
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• pp.15-23
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• 2008

This paper proposes the new structural MOQ(Multiple Input/Output-Queued) switch which guarantees QoS while maintaining high efficiency and deals with the Anti-Empty algorithm which is new arbitration algorithm to be used for the proposed switch. The new structure of the proposed switch based on MIQ, MOQ is designed to have the same buffer speed as the external line speed. Also, the proposed switch makes it possible to remove the weak point of existing methods and introduces the new method of the MOQ operation to support QoS. Therefore, this switch is equal to the Output Queued switch in efficiency and delay, and guarantees the high-speed switching supporting QoS without cell loss.