• Title/Summary/Keyword: Information input algorithm

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An Efficient String Matching Algorithm Using Bidirectional and Parallel Processing Structure for Intrusion Detection System

  • Chang, Gwo-Ching;Lin, Yue-Der
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.4 no.5
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    • pp.956-967
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    • 2010
  • Rapid growth of internet applications has increased the importance of intrusion detection system (IDS) performance. String matching is the most computation-consuming task in IDS. In this paper, a new algorithm for multiple string matching is proposed. This proposed algorithm is based on the canonical Aho-Corasick algorithm and it utilizes a bidirectional and parallel processing structure to accelerate the matching speed. The proposed string matching algorithm was implemented and patched into Snort for experimental evaluation. Comparing with the canonical Aho-Corasick algorithm, the proposed algorithm has gained much improvement on the matching speed, especially in detecting multiple keywords within a long input text string.

Frequency Synchronization Technique for the Equalization Digital On-Channel Repeater (등화형 디지털동일채널중계기의 송수신 신호 간 주파수 동기화 기술)

  • Lee Yong-Tae;Eum Ho-Min;Park Sung-Ik;Seo Jae-Hyun;Kim Heung-Mook;Kim Seung-Won;Seo Jong-Soo
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.31 no.7A
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    • pp.725-733
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    • 2006
  • In this paper, we propose an algorithm which makes the frequency of output signal synchronize with frequency of input signal in Equalization Digital On-channel Repeater (EDOCR) system which was proposed to overcome the disadvantage of conventional Digital On-Channel Repeater (DOCR). Also, we verify the algorithm by using the mathematical equivalent model and analysis the performance by implying the algorithm to EDOCR. The main idea is to use the frequency offset information, which comes from carrier recovery in the receiving part of EDOCR, when the demodulated symbol is re-modulated in transmitting part. Based on the proposed algorithm, EDOCR not only makes the output signal synchronized with input signal in frequency but also emit the output signal which satisfies the ATSC transmission standard without additional equipments such as Global Positioning System (GSP).

A Rule-Based Stereo Matching Algorithm to Obtain Three Dimesional Information (3차원 정보를 얻기 위한 Rule-Based Stereo Matching Algorithm)

  • 심영석;박성한
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.27 no.1
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    • pp.151-163
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    • 1990
  • In this paper, rule-based stereo algorithm is explored to obtain three dimensional information of an object. In the preprocessing of the stereo matching, feature points of stereo images must be less sensitive to noise and well linked. For this purpose, a new feature points detection algorithm is developed. For performing the stereo matching which is most important process of the stereo algorithm, the feature representation of feature points is first described. The feature representation is then used for a rule-based stereo algorithm to determine the correspondence between the input stereo images. Finally, the three dimensional information of the object is determined from the correspondence of the feature points of right and left images.

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Adaptive Digital Predictive Peak Current Control Algorithm for Buck Converters

  • Zhang, Yu;Zhang, Yiming;Wang, Xuhong;Zhu, Wenhao
    • Journal of Power Electronics
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    • v.19 no.3
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    • pp.613-624
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    • 2019
  • Digital current control techniques are an attractive option for DC-DC converters. In this paper, a digital predictive peak current control algorithm is presented for buck converters that allows the inductor current to track the reference current in two switching cycles. This control algorithm predicts the inductor current in a future period by sampling the input voltage, output voltage and inductor current of the current period, which overcomes the problem of hardware periodic delay. Under the premise of ensuring the stability of the system, the response speed is greatly improved. A real-time parameter identification method is also proposed to obtain the precision coefficient of the control algorithm when the inductance is changed. The combination of the two algorithms achieves adaptive tracking of the peak inductor current. The performance of the proposed algorithms is verified using simulations and experimental results. In addition, its performance is compared with that of a conventional proportional-integral (PI) algorithm.

Reconfigurable Intelligent Surface assisted massive MIMO systems based on phase shift optimization

  • Xuemei Bai;Congcong Hou;Chenjie Zhang;Hanping Hu
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.18 no.7
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    • pp.2027-2046
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    • 2024
  • Reconfigurable Intelligent Surface (RIS) is an innovative technique to precisely control the phase of incident signals with the help of low-cost passive reflective elements. It shows excellent potential in the sixth generation of mobile communication systems, which not only extends wireless coverage but also boosts channel capacity. Considering that multipath propagation and a high number of antennas are involved in RIS in assisted mega multiple-input multiple-output (MIMO) systems, it suffers from severe channel fading and multipath effects, which in turn lead to signal instability and degradation of transmission performance. To overcome this obstacle, this essay suggests an improved gradient optimization algorithm to dynamically and optimally adjust the phase of the reflective elements to counteract channel fading and multipath effects as a strategy. In order to overcome the optimization problem of falling into local minima, this paper proposes an adaptive learning rate algorithm based on Adagrad improvement, which searches for the global optimal solution more efficiently and improves the robustness of the optimization algorithm. The suggested technique helps to enhance the estimate of channel efficiency of RIS-assisted large MIMO systems, according to simulation results.

Hierarchical Circuit Extract Algorithm for VLSI Design Verification (VLSI의 설계검증을 위한 계층적 회로 추출 알고리듬)

  • 임재윤;임인칠
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.25 no.8
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    • pp.998-1009
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    • 1988
  • A Hierarchical Circuit Extract Algotithm, which efficiently extract circuits from VLSI mask pattern information, is programmed. Quad-tree is used as a data structure which includes various CIF circuit elements and instances. This system is composed of CIF input routine, Quad-tree making routine, Transistor finding routine and Connection list making routine. This circuit extractor can extract circuit with hierarchical structure of circuit. This system is designed using YACC and LEX. By programming this algorithm with C language and adopting to various circuits, the effectiveness of this algorithm is showed.

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On the Signal Power Normalization Approach to the Escalator Adaptive filter Algorithms

  • Kim Nam-Yong
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.31 no.8C
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    • pp.801-805
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    • 2006
  • A normalization approach to coefficient adaptation in the escalator(ESC) filter structure that conventionally employs least mean square(LMS) algorithm is introduced. Using Taylor's expansion of the local error signal, a normalized form of the ESC-LMS algorithm is derived. Compared with the computational complexity of the conventional ESC-LMS algorithm employs input power estimation for time-varying convergence coefficient using a single-pole low-pass filter, the computational complexity of the proposed method can be reduced by 50% without performance degradation.

Learning Generative Models with the Up-Propagation Algorithm (생성모형의 학습을 위한 상향전파알고리듬)

  • ;H. Sebastian Seung
    • Proceedings of the Korean Information Science Society Conference
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    • 1998.10c
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    • pp.327-329
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    • 1998
  • Up-Propagation is an algorithm for inverting and learning neural network generative models. Sensory input is processed by inverting a model that generates patterns from hidden variables using top-down connections. The inversion process is iterative, utilizing a negative feedback loop that depends on an error signal propagated by bottom-up connections. The error signal is also used to learn the generative model from examples. the algorithm is benchmarked against principal component analysis in experiments on images of handwritten digits.

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MIMO-OFDM Receiver Algorithm with the Capability of Inter-cell or Inter-sector Interference Cancellation (인접 셀 혹은 인접 섹터 간섭제거 능력을 갖는 MIMO-OFDM 수신 알고리즘)

  • Ko, Kyun-Byoung
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.46 no.4
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    • pp.1-7
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    • 2009
  • In this paper, the author presents the MIMO(Multi-Input Multi-Output) receiver algorithm with the capability of inter-cell or inter-sector interference cancellation over multi-antenna OFDM(Orthogonal Frequency Division Multiplexing) systems. As contrast with the previous research dealing with the filtering scheme at the time domain, the proposed algorithm is presented as the pre-filtering scheme which can be applicable to the frequency domain. Note that the proposed one can be implemented only by pilot symbols which are used in the channel estimation. In addition, it is analytically confirmed that the proposed scheme can be applied for either MIMO( C-SM(Collaborative-Spatial Multiplexing)) interference or SIMO(Single-Input Multi-Out) interference. The proposed receiver algorithm is verified by simulations over UL-PUSC SR off in IEEE 802.16e standard. From simulation results, it is confirmed that the proposed one can be applicable regardless of the kind of interference. Furthermore, it is verified that the performance is guaranteed even under Ole severe effect of interference and the improvement of system throughput is guaranteed.

A Design of an Area-efficient and Novel ATM Scheduler (면적 효율적인 독창적 ATM 스케줄러의 설계)

  • Sonh Seung-Il
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.10 no.4
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    • pp.629-637
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    • 2006
  • Currently the research on input-queued ATM switches is one of the most active research fields. Many achievements have been made in the research on scheduling algorithms for input-queued ATM switches and also applied in commerce. The scheduling algorithms have the characteristics of improving throughput, satisfying QoS requirements and providing service fairly. In this paper, we studied on an implementation of scheduler which arbirates the input-queued ATM switches efficiently and swiftly. The proposed scheduler approximately provides 100% throughput for scheduling. The proposed algorithm completes the arbitration for N-port VOQ switch with 4-iterative matching. Also the proposed algorithm has a merit for implementing the scheduling algorithm with 1/2 area compared to that of iSLIP scheduling algorithm which is widely used. The performance of the proposed scheduling algorithm is superior to that of iSLIP in 4-iterative matching. The proposed scheduling algorithm was implemented in FPGA and verified on board-level.